# Generating a desired pulse train in Xilinx ISE software

Need some help with VHDL and FPGA since I am new to it.

I have a Virtex-4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will be like "1011100111000110" (min pulse width = 30 ns).

To be very precise wish to generate this pulse train and send it to a IO pin of FPGA so that I can observe it on scope. Also I don't want to send any input signals (such as input :std_logic_vector(15 downto 0)) except for clock and load. So I am wondering if I can write a VHDL code that is synthesizable and will give the desired output (with any approach such as FSM or counter or shift register).

• "...with any approach such as FSM or counter or shift register". Yes any of your three approaches is likely to work at 33 MHz. Do you have a specific question? – user8352 Jul 17 '14 at 0:48
• Thanks David, I got my desired outcome with the use of shift register. – vhdlnovice Jul 18 '14 at 23:01

I would use a shift register - use a constant to initialise it to your desired pulse train when reset is asserted and then just clock it out. Your top-level entity will only need three pins, clock, reset and the output.