Need some help with VHDL and FPGA since I am new to it.
I have a Virtex-4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train will be like "1011100111000110" (min pulse width = 30 ns).
To be very precise wish to generate this pulse train and send it to a IO pin of FPGA so that I can observe it on scope. Also I don't want to send any input signals (such as
input :std_logic_vector(15 downto 0)) except for clock and load. So I am wondering if I can write a VHDL code that is synthesizable and will give the desired output (with any approach such as FSM or counter or shift register).