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I need to design a schematic for a register that has an input of clk and i[7:0] which is an 8 bit binary input interpreted as a number and an output of F which goes high if i was equal was to 127 base 10 two rising edges ago, and is '0' otherwise. Now I have designed the register having 8 flip flops connected to 8 buses for the input and 8 buses for the output.

How would I go about satisfying the output of F however? I don't understand how to separate the 8 different inputs and outputs, or how an 8 bit output can be represented as a single bit. How would I show 127 base 10 two rising edges ago? I am using Xilinx. Thank you!

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  • \$\begingroup\$ Check if the value is 127. Delay the result 2 clock cycles. \$\endgroup\$
    – Ignacio Vazquez-Abrams
    Jul 19, 2014 at 1:57
  • \$\begingroup\$ There will not be an 8 bit output, only 1 bit. The 8 bits of input will go to an 8 bit comparator whose comparing value is 127. So if input is 127, output bit is set to 1. \$\endgroup\$
    – KharoBangdo
    Jul 19, 2014 at 6:00

1 Answer 1

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If I understand what you're asking for, you want to detect the occurrence of binary 0111 1111 and then report that the occurrence was detected two clocks earlier.

This should do it for you, where the all-ones state is detected by U5, and the two clock delay is generated by U6A and B.

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