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Can a high EMI PCB track under a transistor or diode package (in this case TO247AC) be a problem?

full-bridge PCB layout

To get a better understanding:

full-bridge PCB render image

Is there any advantage on putting these tracks on the other side (like the image above)?

full-bridge PCB render image

If these two options might present problems, what would be a good idea? making a "bus" vertical to the board? Using wires (really great dimensioned to reduce stray inductance)?

The same for the diodes:

rectifier PCB layout

Note: The transistor case is common to collector, so in two of the switches the PCB track under it is common to the case and I think this is not a big problem. But the other two don't.

Some information about the voltage and current:

  • DC Link voltage: ~340V.
  • PEAK current at the IGBT: 75A (at full load on the peak of the switching waveform).
  • Rectified secondary voltage: maximum of 25V/200A at full-load, and 60V at "no-load".
  • Switching frequency: ~20Khz maybe a bit more if the switching becomes so audible.

The edges will be rounded, it's just not the final design yet.

The BUS tracks although not easy to see is one on each side, so to reduce inductance and add capacitance, also giving a nice design and space use, based on http://xellers.wordpress.com/2013/03/14/general-purpose-h-bridge-inverter/. Thanks.

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  • \$\begingroup\$ How do you define "high EMI"? These traces are pretty large and as such, they are going to have large capacitance values. If a fast switching signal is to go through them, this capacitance might effect the signal. As you mentioned, these transistors have a huge metal plate on their back which is the collector and it seems the large traces are also the collector so I don't think they will be affected. I'm only concerned about general signal integrity. It might be worth it spinning a small prototype board and testing it. \$\endgroup\$
    – Evan
    Jul 21, 2014 at 14:39
  • \$\begingroup\$ @EvangelosEm I will define as high dv/dt and di/dt. The traces as I know should be large (width) and shorter in length to lower the inductance, this is by far a concern than the capacitance. The traces as explained are not common to all transistors collectors. This traces are of lower width than the working circuit you can access at the link in the last paragraph of the question. \$\endgroup\$ Jul 22, 2014 at 2:12
  • \$\begingroup\$ I have no experience with this type of application and I might be ignorant of some subtlety of the project so take this with a grain of salt. After taking a look at the application, it seems you won't really mind if the board becomes an unintentional transmitter. Signal integrity doesn't seem to matter either. I would only have the traces on opposite sides on the board just for the larger clearance and creepage since you will be using high voltage/current. This is also suggested by the article you linked, if you look closely at the pictures. \$\endgroup\$
    – Evan
    Jul 22, 2014 at 20:54
  • \$\begingroup\$ @EvangelosEm Thanks. The project I linked is just about the full-bridge and the board. My project does not involve a step-up transformer, but a step-down. The secondary potential will be at full-load 25V or a bit more with 200A (peak of 250A). No load of 60V maximum. This is for a welding machine, so its enclosed and EMI can be reduced to the outside. \$\endgroup\$ Jul 22, 2014 at 22:22
  • \$\begingroup\$ EMI means Electromagnetic Interference. A track will never be a "HIGH EMI track" It doesn´t make sense at all. A track features can be: High switching track, high power track, high impedance... but never high EMI. Please, rewrite your question. \$\endgroup\$ Jul 23, 2014 at 11:15

2 Answers 2

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There are two transients to consider:

  1. High dV/dt: these occur on the switching node (emitter of high-side IGBT and collector of low-side IGBT), each time you switch either IGBT. A high dV/dt can couple to neighboring traces capacitively. If the neighboring trace terminates to a high impedance node (eg. the input to a comparator for current sensing), the capacitive current spike would cause a voltage spike. For a comparator, that could mean a spurious trigger.

A solution is to minimize the overlap area of high dV/dt nodes with sensitive nodes.

In your PCB layout (top image), the upper and lower blue traces are the nodes that see high dV/dt. Since these overlap with nothing, I don't see any issue. It doesn't matter whether they are on the top or bottom planes.

  1. High dI/dt: this happens when the current switches from the high side to low side or vice versa. High dI/dt can result in a couple of issues: a. Result in a voltage drop across parasitic inductance that is in the path of the current b. Induce a voltage in neighboring traces.

A solution to (b) is to minimize the area of all high current loops, and hence minimize the side-by-side trace lengths of high dI/dt nodes and sensitive ones.

Given your configuration where the TO-247AC package (plastic/mold compound) contacts the solder mask, the closest electrically conductive nodes to your PCB traces are the bondwires inside the package that loop over from the leadframe to the die. These wires are tiny, and depending on the metal type no more than 10's of mils in diameter, coming close to the surface of the package [1]. So the overlap area is negligible.

[1] Nice photo of the pre-molded TO-247: http://www.power-eetimes.com/imf/c/eyJtYXNrIjoiNDMyeDI4OCJ9/images/01-edit-photo-uploads/2014/2014-06-june/onsar2662_fig-1.jpg

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  • \$\begingroup\$ Thanks. As other responses I already know that, the DC BUS is layered to reduce stray inductance and add capacitance. The parasitic inductance on the upper and lower traces are minimized by higher track width and lower length (if considering only these an approximation calculation of the stray inductance of each will be near 30nH). As will see the transformer is not on the PCB so there wires to the transformer that will present stray inductance too (twisting the wires will cancel much of the inductance and add capacitance). The high voltage spike is more a concern to the switching devices than \$\endgroup\$ Jul 30, 2014 at 7:15
  • \$\begingroup\$ to other components (but thanks for nothing that on other components its true). This high voltage spike is reduced by good snubber. \$\endgroup\$ Jul 30, 2014 at 7:16
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    \$\begingroup\$ @DiegoCNascimento Looks like 20vero isn't responding. There shouldn't be any noticeable, if any at all, parasitic effects. The internals of the transistors and diodes will not effect anything in those tracks since neither generate a primary magnetic field. If they were inductors, that'd be a different story. If you are so worried any problems though, It would be beneficial to place the tracks on the other side to get a good amount of space between the components internals and the tracks. That would mitigate any parasitic effect on the tracks by the components. \$\endgroup\$
    – Funkyguy
    Jul 30, 2014 at 16:42
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    \$\begingroup\$ I'm not on SE full-time :). Agree with @Funkyguy. I can add that I work on the packaging of more complex modules with multiple silicon die. Given your configuration (plastic/mold compound) "touching" the solder mask, the closest electrically conductive nodes to your PCB traces are the bondwires inside the TO-220 package that loop over coming close to the surface of the TO-220. These are tiny (diameter in single digit mils) so the overlap area is negligible. \$\endgroup\$
    – 2over0
    Jul 30, 2014 at 18:57
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    \$\begingroup\$ @DiegoCNascimento Make sure you give the bounty to 20vero \$\endgroup\$
    – Funkyguy
    Jul 30, 2014 at 19:00
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You question regards basic signal integrity principles.

You will want to avoid sending tracks through vias as much as possible since as frequency increases, vias will cause reflects on the traces which will introduce an new noise source. The only one I would say is okay to send through vias is the connections to the GND plane and connections going to a POWER plane. Apart from that, keep signals away from vias.

With that said, routing thick traces in parallel will introduce a parasitic capacitance between the two, although if you are working with the 20khz frequency, I don't see too much of a problem with the parasitics.

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    \$\begingroup\$ Did you read the question? Its about the high di/dt and dv/dt tracks under the IGBT package. The two tracks of the DC-BUS are designed TO HAVE a capacitance and reduce stray inductance. The legs top-bottom tracks seems a bit distance to make a significant capacitive coupling, there are papers that say to have them even close so that the opposing currents cancels the effect. Also I didn't use vias to router the power signals, the package is thought hole so the pads will make a via anyway. \$\endgroup\$ Jul 25, 2014 at 3:01
  • \$\begingroup\$ Ah yes, well it would help if you clarified that in the question a bit better and then left a friendly comment asking me to revise my answer to better fit what you are asking for \$\endgroup\$
    – Funkyguy
    Jul 25, 2014 at 4:45
  • \$\begingroup\$ Sorry, the comment is friendly. I just repeated some of the things that are already in the question, that's why it sounds a bit non-friendly. \$\endgroup\$ Jul 26, 2014 at 3:08

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