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The is the simulated version of the schematic. Schematic protection circuit

I have designed a protection circuit for my pcb and I would appreciate having some feedback before starting the PCB design.

The circuit is broken down as follow;

-ESD protection provided by a one channel IC

-low pass filter to suppress noise above 4.5Khz

-pmos to protect against reverse polarity

-crowbar for overvoltage protection

-current sensor which is connected to a uC ( ideally I would like the op amp to work with the PSU IN in the range 3.3v to 16v)

The maximum voltage is 16V and the minimum votlage is 3.3V.

Final schematic protection circuit

The is the final version of the schematic

Edit:

I have modified the current sensing part, fixed the short circuit issue with R(sense). PSU out is from node R (Load). I am using the PSU IN to power the OP AMP and added a decoupling capacitor. enter image description here

Edit 2:

enter image description here

The current monitored is in the range of 0 - 1A . ADC is from 0 - 3.3V

The actual models used have been implemented in the schematic for clarity.

The supply voltage range is from 3.3V to 16V

The low pass filter has been replaced by a ferrite bead

Differential Op amp is used for current monitoring with 165K for R load to provide the adequate gain (0 to 3.3V input to the ADC).

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    \$\begingroup\$ You do understand, I hope, that that R5 is going to pull 34 anps at 16 volts? \$\endgroup\$ – WhatRoughBeast Jul 21 '14 at 10:54
  • \$\begingroup\$ I was wrong about R5. It is protected by Q1. In addition, the gate threshold for the PMOS can be as high as 4 volts, so it may not turn on at 3.3 volts. Even if it does, since it is always on, why is it there? And since its RDSon is 30 ohms, it will pretty much die instantly due to the small value of R5 at 16 volts (it will dissipate about 9 watts in a small package). \$\endgroup\$ – WhatRoughBeast Jul 21 '14 at 11:13
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    \$\begingroup\$ @WhatRoughBeast: The PMOS transistor will cut off if reverse voltage is applied to the input. This is a common idiom for low-voltage equipment. Of course, the input voltage must remain within the V_gs limits at all times. \$\endgroup\$ – Dave Tweed Jul 21 '14 at 11:50
  • \$\begingroup\$ I think R5 is not supposed to be a load, but to be the current sensing device. PSU OUT is tied to the wrong node, and R5 should not go to ground. \$\endgroup\$ – Vladimir Cravero Jul 21 '14 at 13:03
  • \$\begingroup\$ @VladimirCravero : Please have a look at the edited version of the circuit. \$\endgroup\$ – user49395 Jul 21 '14 at 13:44
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Despite several requests for detailed requirements, not nearly enough has been forthcoming, and it has been requested "What I am looking for is feedback regarding the circuit itself, addition of decoupling capacitors, impedance matching problems, timing problems etc.. not the models themselves". Well, I'll do my best. What requirements are known are

-ESD protection provided by a one channel IC

-low pass filter to suppress noise above 4.5Khz

-pmos to protect against reverse polarity

-crowbar for overvoltage protection

-current sensor which is connected to a uC ( ideally I would like the op amp to work with the PSU IN in the range 3.3v to 16v)

The maximum voltage is 16V and the minimum votlage is 3.3V.

So let's take it step by step.

ESD protection. Since the schematic parts are not necessarily what will be used, this is a bit tricky, but let's stick with the schematic, and specify a TPD1E10B09. Data sheet is here http://www.ti.com/lit/ds/symlink/tpd1e10b09.pdf. The most obvious problem is that it acts as a bilateral 12 volt zener, as shown in Fig. 5. Since this is an 0402 package, it will be destroyed by any sort of input above 12 volts. 16 volts is not an option.

Low-pass filter. This is a pi filter with two 47 uF caps and a 27 uH inductor (inductor resistance unspecified). Since the PSU input can be assumed to be very low resistance (it's a power supply output), the first capacitor is essentially irrelevant. The resulting L filter does indeed roll off after about 4.5 kHz. However, its response looks like enter image description here and is not what I would recommend to get rid of noise. That's a gain of more than 1000 at 4.2 kHz. The peak can be eliminated by adding a 1 ohm resistor in series with the inductor.

Crowbar. This uses a 1N750 zener and a C233 SCR. The zener has a knee voltage in the range of 4.5 to 4.9 volts, and the SCR is guaranteed to fire with a gate voltage of 1.5 volts and 9 mA. The result is a crowbar voltage of as much as 6.4 volts. If this is adequate to protect the pcb, fine. However, without knowing the characteristics of the power supply providing the power into the PSU IN, it is not clear what will happen to the 27 uH inductor if the crowbar activates. Smoke and flame is a real possibility. ETA - This is wrong. The fuse will protect the inductor. Sorry.

PMOS reverse bias protection. A p-type MOSFET is used. Again, there is no indication of exactly which MOSFET will actually be used, and the schematic unit is clearly unsuitable, so let's assume something like an IRF9530. With a 3.3 ohm load (allowing 1 amp at 3.3 volts output, the circuit was simlulated for a 0-5 volt input: enter image description here Green is input, brown is output. A 3.3 volt input will only produce a 1.4 volt output, so maybe some rethinking is in order.

Current sensor. It was later specified that the current monitor output should be in the range of 0 - 3.3 volts, but the maximum current level was not specified. The schematic circuit shows a voltage amplifier with a gain of 7. 3.3 volts / 7 equals .47 volts. The resistor which is obviously intended to be the sense resistor has a value of .47 ohms, leading to the conclusion that the desired current sense range is 0 - 1 amp. The schematic circuit simply does not measure current, so the following is offered

schematic

simulate this circuit – Schematic created using CircuitLab

This is a standard difference amplifier with a gain of 7, in line with the original. The op amp is powered by the PSU input, with a 10 ohm / 10 uF power filter. While an appropriate op amp can, I'm sure, be procured, there are a few things to remember. The opamp does not need to be rail-to-rail at the input. The power supply, due to the ESD clamp, will not get above about 12 volts.

However, I cannot recommend this circuit. The 0.47 ohm sense resistor will drop .47 volts when the current is one amp. Adding this to the drop in the PMOS section, the 1 volt drop produced by the damping resistor in the low-pass filter, and the unspecified drop in the fuse, a full-scale current will produce an awful lot of voltage drop. (Speaking of fuses, a Littlefuse series 208 2AG fuse rated at 1 amp has a cold resistance of 0.103 ohms.) A better approach would be to use a smaller sense resistor and a larger gain in the difference amplifier.

To sum it up, I am dubious about every part of the circuit.

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  • \$\begingroup\$ I have provided the real models used and modified the current sensing part of the circuit among other small things. \$\endgroup\$ – user49395 Jul 22 '14 at 14:20
  • \$\begingroup\$ That is better. I would recommend, though, a 0.1 to 1 uF bypass cap on the INA168 power. Also, your ESD protector will attempt to clamp the input to 5 volts, and will be destroyed by any significantly greater voltage. 16 volts is even less possible than before. \$\endgroup\$ – WhatRoughBeast Jul 22 '14 at 14:32
  • \$\begingroup\$ May I ask where in the datasheet have you seen the 5 volts value for the clamp? I have the following ; Clamping Voltage Vc Max: 28V Operating Voltage: 3.3V \$\endgroup\$ – user49395 Jul 22 '14 at 14:43
  • \$\begingroup\$ You are looking a infineon.com/dgdl/…, Table 5, right? Note that the test condition for Vcl is 16 amps. A better method is to see what it will take to draw 1 amp. Since Vbr is 5 volts, and Rdyn is about .5 ohms, 5.5 volts will cause the device to draw 1 amp, and it will attempt to dissipate 5.5 watts - which ain't gonna happen. \$\endgroup\$ – WhatRoughBeast Jul 22 '14 at 14:48
  • \$\begingroup\$ Also, I note that your crowbar zener, a MMB5247B, has a knee voltage of 17 volts. Are you really willing to set your crowbar voltage that high? And even if you are, this is perilously close to your intended clamp voltage on the ESD protection. You need some margin, whatever you go with for ESD. Make the crowbar well under the ESD clamp, or you may kill the ESD device. \$\endgroup\$ – WhatRoughBeast Jul 22 '14 at 14:52
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works well after simulation as well.

Well, no. Your op amp is configured as a non-inverting gain of 7. Its inputs (pins 5 and 6) have, according to your last schematic, 2.5 and .5 volts on them. Does this not tell you that you have a problem? For an opamp operating normally, the difference between the inputs will be microvolts.

Your simulation appears to be using a 3.3 volt input, judging from the 2.49 volt level appearing after the voltage drops resulting from the PMOS, the inductor and the fuse. Why do think that an ADC output of 3.8 volts is appropriate?

Your R11 is lableled as load. Does this mean that you are going to all this trouble to drive a 1k load?

Please start from the beginning. Tell us what your expected load is and what you hope to measure (voltage or current). Tell us what range of voltage you need to drive your ADC.

As it stands, for instance, if your PSU output drives a 1 amp load, your PMOS transistor will dissipate 30 watts - as it vaporizes.

As another problem, the OP471 is a good op amp - I've used it often. It is not even remotely suited to single-supply operation at 3.3 volts. It is intended for +/- 15 volts, with +/- 5 as a minimum.

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  • \$\begingroup\$ the inverting input of the OPAMP is connected to ground and the non inverting part is sensing the voltage across Rsense. What I am trying to do is to monitor the current on my uC using ADC. The OP AMP is used only to provide a gain to have a readable range. \$\endgroup\$ – user49395 Jul 21 '14 at 19:33
  • \$\begingroup\$ The models provided on the schematic are not the ones I will be using on my PCB, this was only for the sake of testing that the circuit works, so please ignore the voltage drops and unreasonable power dissipated. The 1K resistor is simply for simulations purposes. The range of the ADC is from 0 to 3.3V. Similarly for the OP AMP I am not using the 471. \$\endgroup\$ – user49395 Jul 21 '14 at 19:34
  • \$\begingroup\$ What I am looking for is feedback regarding the circuit itself, addition of decoupling capacitors, impedance matching problems, timing problems etc.. not the models themselves. \$\endgroup\$ – user49395 Jul 21 '14 at 19:36
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    \$\begingroup\$ I cannot give you feedback if you keep me in the dark as to what you expect. For instance, what range of current are you trying to measure? The circuit itself won't work. Yet you say "I don't see how that's wrong. works well after simulation as well." and then you admit that the models you are using aren't what you will really use, so you ignore the fact that the models you are using cannot work even though you claim they do. This is really, really frustrating. \$\endgroup\$ – WhatRoughBeast Jul 21 '14 at 20:39
  • \$\begingroup\$ I don't know how you can make head or tails of that schematic. It looks to me like the non-inverting input is connected to PSU in. Right, and then get's gained up by a factor of 7. And the OP says the inverting input is connected to ground! Dat won't work. Oh and if not an OP471 what opamp are you using? \$\endgroup\$ – George Herold Jul 21 '14 at 21:06

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