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I want to build something like UM232H-B Breakout Module. This configuration uses an FT232H, to convert usb to serial/parallel. I don't know whether it works with FPGA parallel port programming cable or not.

Is it possible to use this configuration instead of parallel ports to program a XILINX FPGA? and Does this configuration work with XILINX's ISE?

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The free xc3sprog project ( http://xc3sprog.sourceforge.net ) supports loading Xilinx FPGA firmware through FT232H / FT2232H / FT4232H. This is not officially supported by Xilinx, but does seem to be pretty well supported by the community. (Supported device list: http://sourceforge.net/p/xc3sprog/code/HEAD/tree/trunk/devlist.txt )

Xilinx ISE (Impact) does not support this hardware directly, but you can write a small batch file or shell script to pass your firmware bitstream file to xc3sprog. This helps save a lot of typing and mistyping.

If you're bothered by the lack of official Xilinx support, or you opt to purchase a solution instead, digilentinc.com (an official Xilinx partner) offers some low-cost USB-JTAG modules (based on FT2232H I think) and free programming software. Sadly they have kept their USB-JTAG module circuit proprietary, but xc3sprog + FT232H is a great open-source alternative.

(The FT232H / FT2232H / FT4232H also support general bit-banging; consult the D2XX Programmer's Guide at http://www.ftdichip.com/Support/Documents/ProgramGuides.htm )

Checking the JTAG Connections

The FTDIchip.com USB interface chips FT232H, FT2232H, or FT4232H can be connected to Xilinx JTAG pins as follows:

AD0 = TCK
AD1 = TDI
AD2 = TDO
AD3 = TMS

For FT2232H you can use BD0, BD1, BD2, BD3 as an alternate connection.

Example command to check whether the JTAG connections are working:

xc3sprog.exe -L -c bbv2_2

Expect response (for example with Spartan-3AN 700 FPGA, other chips have different IDCODE values):

JTAG loc.: 0    IDCODE: 0x22628093  Desc:       XC3S700AN   Rev: C  IR 

The first time you try to get this working, you will have to determine which cable type you have connected. My examples use cable type -c bbv2_2 i.e. the second port of the FT2232H since that's what I have used on my custom FPGA board. AD0-AD7 go to my FPGA for communications, and BD0-BD3 go to JTAG. For the single-port FT232H I think you want to use -c ft232h instead of -c bbv2_2 . See cablelist.txt for the list of choices.

FPGA Trial Configuration

Once you have verified that xc3sprog can see your USB interface chip and also can see the FPGA on the JTAG scan chain, then you can load a firmware bitstream file (e.g. top.bit).

Example command to load a bitstream ( ms-dos batch file variable %filename_dot_bit% ):

xc3sprog.exe -L -c bbv2_2 -v %filename_dot_bit%

This is great for development work, where you just want to load a new configuration bitstream directly into the FPGA over JTAG. But when you want to store the bitstream on non-volatile memory (so that the program runs when power is first applied), you need to use a two-stage process that first loads a boundary-scan bitstream.

Supporting Active Serial SPI Configuration Memory

Assuming your board is configured for Active Serial SPI boot from an SPI flash memory (such as M25P), xc3sprog supports this type of loading as well. The first stage loads the FPGA with a boundary-scan support bitstream known as bscan_spi, which gives JTAG access to the SPI port that the configuration memory is connected to, then the second stage loads the configuration memory.

When setting this up for the first time, create a new project targeting your FPGA. Since configuration bitstreams are not portable to different size FPGA, the actual project filename should reflect the specific target FPGA model, size, and package (like xc3s700an.bit or xc6slx16_cs324.bit). Example source code is provided in the bscan_spi subdirectory when you download the source code from sourceforge. This subdiretory also contains prebuilt bscan_spi bitstreams for several commonly used FPGAs. You need one of the verilog sources, such as bscan_s3_spi_isf.v (spartan-3) and one UCF user constraints file to specify the FPGA pin locations where the active serial SPI configuration memory is connected.

For my board, I customized the bscan_spi code to put on a chaser light show with the LEDs, to visually indicate that the board was busy programming its on-board flash.

Writing SPI Configuration Memory

The commands for this two-stage loading are like this:

@REM Temporarily load boundary scan support firmware
xc3sprog.exe -L -c bbv2_2 -v %bscan_spi_bit%
@REM Now program the flash
xc3sprog.exe -L -c bbv2_2 -v -I %filename_dot_bit% -R

If you are deploying this setup to customers so that they can update the FPGA 'in the field', you just provide the customer with:

1. xc3sprog.exe
2. the bscan_spi bitstream specific to your FPGA
3. your FPGA bitstream
4. batch file or shell script for launching xc3sprog
5. device driver for FTDIchip.com (if customer has very old system where FTDI driver not already built-in)
6. readme.txt file that instructs them to plug in the USB cable and run the batch file

In the real batch files, I also do some additional checking to throw an actionable error message if any of the required files are missing. Omitted to streamline the answer.

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  • \$\begingroup\$ What is bscan_spi.bit? and How can I generate it? Is it possible to program XCF04S with bscan_spi? \$\endgroup\$ – SMA.D Sep 1 '14 at 10:52
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    \$\begingroup\$ The bscan_spi boundary scan bitstream is compiled to run on the target FPGA, so the real filename will be something specific to the FPGA, like xc3s700an.bit or xc6slx16_cs324.bit -- the common source code is in the source code bscan_spi subdirectory. \$\endgroup\$ – MarkU Sep 1 '14 at 20:47
  • \$\begingroup\$ @SMA.D edited to clarify how to build bscan_spi support bitstream. Hope this helps. \$\endgroup\$ – MarkU Sep 1 '14 at 21:52

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