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I am using a MC100EP016A IC which is an 8-bit synchronous binary up counter.

According to the specifications of the IC, you could use either single ended or differential clock input for the counter.

For the differential input mode, the parameter specified is:

Input high voltage common mode range

I do not understand what this represents. Can somebody help?

It says that the Input high voltage common mode range is min 2V and max 3.3 volts. What does this mean?

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    \$\begingroup\$ You've got to stop using all-caps and misusing normal capitalization and punctuation or you're not going to get good help. \$\endgroup\$ – JYelton Jul 26 '14 at 19:06
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The most positive input of the differential pair must be within that voltage range.

In the case of this chip, it varies from Vee+2.0V to Vcc, so for a 3.3V Vcc (PECL) it will be 2V ~ 3.3V.

(the diagram below is for Vcc = 5.0V rather than 3.3V)

http://www.eetindia.co.in/ARTICLES/2005JUN/A/2005JUN21_TPA_AN.PDF?SOURCES=DOWNLOAD

I don't see Vpp specified in the datasheet for that chip, but it's usually 150-800-1200mV minimum-typical-maximum.

See this link for more.

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  • \$\begingroup\$ What do you mean by "most positive input"? Are the clock signals subtracted, so the magnitude of the difference must reside within this range? That's rather interesting. What is the purpose of driving with both a clock and a /clock? How could you get such a clock? \$\endgroup\$ – sherrellbc Jul 26 '14 at 22:37
  • \$\begingroup\$ It's a differential input. Driven by a differential output. ECL is almost like analog differential amplifiers. \$\endgroup\$ – Spehro Pefhany Jul 26 '14 at 22:43

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