Please correct my understanding.

I understand that in peak current control mode, the slow outer voltage control loop generates a current command to the faster inner current loop. This current command places a limit on how much current can flow through the inductor. The switch is turned off as soon as the sensed inductor current hits the ceiling. Any swing in line voltage is thus accounted for in real quick time rather than detecting it via changes in Vout which can take time to manifest.

What exactly is average current control? Is this as simple as generating a current command which is representative of the desired average inductor current rather than the peak current? And as in the above case, as soon as the inductor current hits the average current reference, the switch is turned off. Is this correct?

Why would one choose average current control over peak current control? Kindly explain without without algebra. I regret to say that all literature available on this topic is simply not for the layman.

As am interested in doing this the digital way, I would like to utilize the available ADC, DAC and Analog comparators on my microcontroller. What can be a good algorithm here?

Please advise.

  • \$\begingroup\$ Can you provide a link to average current control? \$\endgroup\$
    – Andy aka
    Commented Jul 27, 2014 at 10:26

1 Answer 1


Yes, average control measures the average current in the inductor and uses that in the inner current loop.

One advantage is that you don't get subharmonic oscillations at duty cycles >50% as you do in peak current mode control (without slope compensation.) Also, the average inductor current is the true state variable that you're trying to control, the peak inductor current is only an approximation. The peak to average ratio changes with operating condition.

Disadvantages are: More complex to measure the average current. Current limit may not be cycle-by-cycle.

For digital control, it's fairly simple. Create a in inner current loop by measuring the average inductor current, and use the outer voltage loop's error to drive the current reference just like you would in analog.

  • \$\begingroup\$ So the algorithm would be as follows: There will be two software loops. First loop is the voltage loop which periodically measures Vout, compares Vout against VRef and generates Vc (also IRef). This would have been the digital equivalent of VEA - Voltage Error Amplifier. The second loop is the digital equivalent of CEA and runs every PWM cycle. It measures IL, compares it with IRef and generates IC (Average Current). This average current determines duty cycle. So no external ramp is needed. 2 ADC channels suffice + 1 PWM timer suffice. Correct? \$\endgroup\$
    – Raj
    Commented Jul 30, 2014 at 6:21
  • 1
    \$\begingroup\$ @Raj You have it exactly correct. You'll want the bandwidth of the current loop to be >> than the bandwidth of the outer voltage loop, so as not to add too much phase lag to the voltage loop. The current loop will then make the inductor "disappear" as far as the voltage loop is concerned and the compensation of the voltage loop will be much easier than if it were voltage mode. \$\endgroup\$
    – John D
    Commented Jul 30, 2014 at 6:49
  • \$\begingroup\$ Thanks a lot John. I have read a lot in other literature about the disappearing inductor, but never quite understood the statement/concept. Can you please (please) explain it in simple terms? \$\endgroup\$
    – Raj
    Commented Jul 30, 2014 at 11:53
  • \$\begingroup\$ @Raj Sure: Since you have a high bandwidth loop controlling the current in the inductor the transfer function of that part of the circuit (as far as the outer voltage loop is concerned) is just a constant- The number of amps per volt that you get with your current control loop (Regardless of the value of L for example). So you have effectively built a current source that drives the output capacitor, and the L*S term doesn't appear in open voltage loop transfer function anymore. (In reality of course there are still effects that you have to consider, but that's the basic idea.) \$\endgroup\$
    – John D
    Commented Jul 30, 2014 at 15:26

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