i know the circuit. I implement it using verilog and it giving result correct. like when we have to design any digital circuit we draw truth table. Optimize circuit using K-map and then implement. In case of edge trigger Flip flop( i am considering the easiest flip flop i.e. D flip flop) . How we draw its circuit using gates?

Negative Edge trigger D flip flop


closed as unclear what you're asking by tcrosley, Michael Karas, Matt Young, Rev1.0, Vladimir Cravero Jul 28 '14 at 9:51

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    \$\begingroup\$ I don't understand. If you know the circuit and you can implement it in verilog, then what's the question? \$\endgroup\$ – clabacchio Jul 27 '14 at 20:04
  • \$\begingroup\$ how this respond only to Falling negative edge. The falling negative edge consider as 1 or 0 ? \$\endgroup\$ – SW. Jul 28 '14 at 4:26
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    \$\begingroup\$ An edge is an edge, neither 1 or 0. If it's falling then it's from 1 to 0. \$\endgroup\$ – clabacchio Jul 28 '14 at 7:25
  • \$\begingroup\$ When clk is in it negative edge then how we determine q? (what is the value of clk that time (0 or 1)) \$\endgroup\$ – SW. Jul 29 '14 at 4:07
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    \$\begingroup\$ This can help, especially the part about edge triggered. \$\endgroup\$ – clabacchio Jul 29 '14 at 5:51