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As you know most of the MCU's has several Vdd and Vss pins. In the case of two-layer PCB it seems convenient to use some polygons beneath MCU (like on the figure below). The first option is treat the top polygon as a ground and bottom as a power. The second option is treat the top polygon as a power and bottom as a ground. There is a third option: don't use two polygons and route power or ground by individual traces even though it's not very easy.

So which options is preferable in terms of a better chance of a good prognosis? Maybe there are other options?

PCB Layout

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    \$\begingroup\$ See this great answer by Olin, it might help you out. \$\endgroup\$ – Vladimir Cravero Jul 29 '14 at 12:59
  • \$\begingroup\$ Such niceties are often hard to achieve with a two-layer board. A power polygon is something I wouldn't bother with. A good uninterrupted copper pour to ground is probably enough, but its good practice to think about the arrangement. Really good treatment at electronics.stackexchange.com/questions/15135/… \$\endgroup\$ – Scott Seidman Jul 29 '14 at 13:02
  • \$\begingroup\$ Aagh, someone posted it while I was searching it up!! \$\endgroup\$ – Scott Seidman Jul 29 '14 at 13:03
  • \$\begingroup\$ Yeap, really great answer, but there is nothing about the z-order of the ground and power planes (I mean beneath the "radiating" or "radiation-sensitive" components like MCU or ADC). Maybe it doesn't matter? \$\endgroup\$ – user11057 Jul 29 '14 at 15:34
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If the part is SMT your best bet is probably to try to put a fairly intact ground pour under the chip (bottom layer) and route most of the traces out of the dense area on the top layer. The power connections can be tied together and bypassed to ground with ceramic capacitors near the chip on the top or under the chip on the bottom. Of course there will be vias near the capacitors either way.

If it's through-hole, it may make more sense to try to route some traces on top and some on bottom, again with bypass capacitors near the chip. A ground pour on the bottom and a Vdd pour on top may make sense, though neither will be very much like a multilayer power plane.

Today's circuits tend to have a lot of different Vdd/Vcc voltages, and sometimes Vee if you're doing mixed signal designs, so a complete power plane covering the entire board is a bit of a dream even with 6 layer boards, let alone two layer.

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    \$\begingroup\$ Why the difference between SMT and through-hole? \$\endgroup\$ – Rocketmagnet Jul 29 '14 at 13:24
  • \$\begingroup\$ @Rocketmagnet The SMT pads are all on one side (usually the 'top') so you'd need to add a trace plus a via to each one you want to route on the bottom layer. Through-hole pads are on both (all if multilayer) layers so you can route them out of the congestion on any layer you like. If you keep the fanout (in the PCB sense, not the logic sense) mostly or entirely on the same layer as the pads you can leave a ground plane mostly intact under the part. It's more like single-sided board layout strategies for SMT boards with a ground pour, whereas for two layer you can use a different strategy. \$\endgroup\$ – Spehro Pefhany Jul 29 '14 at 13:31
  • \$\begingroup\$ @Rocketmagnet With through hole on two layer you can use a strategy with vertical traces mostly on one side and horizontal mostly on the other. \$\endgroup\$ – Spehro Pefhany Jul 29 '14 at 13:34
  • \$\begingroup\$ No, what I meant was: why do you suggest using an intact Gnd plane for SMT, but for TH, you suggest routing some traces under the chip. If anything I would have thought the opposite would be easier due to the multi-layer nature of TH. You can easily have a Gnd plane under a TH chip, but some space constrained SMT designs might need tracks vias under the chip for fan out. Do SMT and TH chips have equal need for a Gnd plane? \$\endgroup\$ – Rocketmagnet Jul 29 '14 at 15:18
  • \$\begingroup\$ @SpehroPefhany Yes, I think you're right about one common power plane, but if we talking about the small local power plane (or individual power traces) and the ground plane (maybe local too) - does it matter the z-order in which they are located under the MCU? \$\endgroup\$ – user11057 Jul 29 '14 at 15:26

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