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I am developing an application based on F28035 with CCSv6. The first version of the software was developed using the Experimenter Kit along with the F28035 ControlCARD.

In the second stage of development, the ControlCARD must be connected on a self-developed hardware. The hardware connection (USB), is based on the same hardware present on the Experimenter Kit (FT2232 - FTDI adapter). When I want to download the software from CCSv6, to the self-developed hardware, I get the following error message:

C28xx: Error connecting to the target: (Error -1135 @ 0x0) The emulator 
reported an error. Confirm emulator configuration and connections, reset the 
emulator, and retry the operation. (Emulation package 5.1.507.0)

Then I ran a connection test from CCSv6, which got the following result:

[Start: Texas Instruments XDS100v1 USB Emulator]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

/home/martin/.ti/ti/0/0/BrdDat/testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'libjioserdesusb.so'.
The library build date was 'May 21 2014'.
The library build time was '13:04:29'.
The library package version is '5.1.507.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 39 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 2 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS100v1 USB Emulator]

In this output, no error report is observed. However, there is a difference from the same test run for Experimenter kit.

In this case (self-developed hardware), the parameter "JTAG IR instruction path-length" is 39 while for the Experimenter Kit is 38, and the parameter "JTAG DR bypass path-length" is 2, while for the Experimenter Kit is 1. I Do not know if this can cause the error, but is the only difference I see between Experimenter Kit and self-developed hardware. Experimenter Kit works fine, self-developed hardware no.

Of course, I checked with an oscilloscope activity in 5 lines of JTAG.

Can anyone suggest any ideas?

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  • \$\begingroup\$ How about circuit diagrams and PCB layouts of both boards. \$\endgroup\$
    – Andy aka
    Jul 29, 2014 at 16:08
  • \$\begingroup\$ Yes. I will upload schematics ASAP. \$\endgroup\$ Jul 29, 2014 at 16:12

1 Answer 1

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The circuit has four optocouplers between the emulator and the controlCARD. These optocouplers are specified as ISO7220A. The problem is that the transmission rate set by default to XDS100v1 (CCSv6) is 1 Mbps and the optocouplers max rate is 1 Mbps. The solution was to reduce the transmission rate. Anyway, an adaptation of the design is imposed, to implement the connection by optocouplers ISO7220C (maximum transmission speed is 25 Mbps).

Thanks @Andyaka for your interest!

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    \$\begingroup\$ This is not an answer, but should be a modification to the original question. \$\endgroup\$ Jul 30, 2014 at 17:40
  • \$\begingroup\$ Please use the edit link on your question to add additional information. The Post Answer button should be used only for complete answers to the question. \$\endgroup\$ Jul 30, 2014 at 18:10
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    \$\begingroup\$ @placeholder: How is this not an answer? Read the sentence beginning, "The solution was ..." \$\endgroup\$
    – Dave Tweed
    Jul 30, 2014 at 18:35
  • \$\begingroup\$ @DanielGrillo. Sorry for my english! The answer is posted to explain the solution I found to the problem, not to add additional information. Again, sorry for my english! \$\endgroup\$ Jul 30, 2014 at 18:37
  • \$\begingroup\$ @DaveTweed fair enough, It is written with additional details, which threw me off. \$\endgroup\$ Jul 30, 2014 at 20:05

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