# VHDL 'buffer' vs. 'out'

I was wondering about the 'buffer' i/o option for entities in the VHDL language. I have found that my code is much cleaner if I use the 'buffer' option instead of 'out' in any circumstance where I want to act on the outgoing signal somewhere within the entity. I find that I can think of very few reasons to use 'out' ever and I'm tempted to just always use 'buffer' in every case. So, my question is, under what circumstances should I set my outputs as 'out' (even when that means I have to add an extra signal declaration and assignment) and when is it ok to use 'buffer'?

• The only 2 problems with buffer are: (1) mixing out on one hierarchical level with buffer on another is disallowed (one way round; can't remember which!) and (2) Some tools produce reams of fussy but meaningless warnings about buffer (but still work anyway!). Buffer is absolutely fine. – Brian Drummond Jul 29 '14 at 21:43
• By "tempted to just always use 'buffer' in every case" do you mean to quit using out-mode ports completely, or only in the cases where you want to read their values from within the design entity? – rick Jul 30 '14 at 4:37
• I should also ask whether your tools support VHDL-2008, in which case you would be able to read out-mode ports without any problem. – rick Jul 30 '14 at 4:38

One case, that probably doesn't apply, is if you're using a standard older than VHDL-2002. Before than, buffer could not connect directly to out. So in a hierarchical design, the signal path would need to be declared as a buffer on all levels. Also, when adhering to these older standards, some tools have problems synthesizing buffers correctly. They may or may not warn you about this.

These should no longer be an issue if you're using a newer standard. From the VHDL-2002 Standard:

a) For a formal port of mode in, the associated actual must be a port of mode in, inout, or buffer.

b) For a formal port of mode out, the associated actual must be a port of mode out, inout, or buffer.

c) For a formal port of mode inout, the associated actual must be a port of mode inout, or buffer.

d) For a formal port of mode buffer, the associated actual must be a port of mode out, inout, or buffer.

e) For a formal port of mode linkage, the associated actual may be a port of any mode.

I also often see advice stating that a buffer should never be tri-stated. If you need the ability to tri-state a bus, then you would need to use out. I could find no direct reference to how buffers handled tri-stating in the standard. But it is probably good advice to follow. Again, your tools may or may not complain if you attempt to synthesis a tri-stated buffer.

• Additionally you could note that in the pre-2002 case a buffer can have at most one source. – user8352 Jul 30 '14 at 0:36
• @DavidKoontz I actually had a similar statement in my answer to begin with, but took it out because I could find no explicit reference in the standard to allowing multiple drivers to a buffer. But that is also good information to have. – embedded.kyle Jul 30 '14 at 13:07