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In Decoupling caps, PCB layout, three variants of placing bypass caps are presented:

Placement

In the comments, it is mentioned that C19 is the worst approach, C18 slightly better and C13 the best way, which is somewhat contrary to my understanding, so I'd like some clarification.

I'd expect the C19 layout to be close to optimal:

  • the capacitor is placed in-line between the vias to the supply planes, so high-frequency components can be filtered out optimally
  • the vias are not too far apart

I'd probably use wider traces between the capacitor and the vias (Altera's AN574 suggests that).

C13 is a bit closer to the IC, but the vias are on the far end of the connection, so I'd expect worse behavior at high frequencies (probably too high to matter, but...)

The C18 layout is the worst:

  • the vias are far apart, increasing inductive impedance
  • the loop is fairly large
  • same issues as C13 with high frequency ripple

Where am I going wrong with my analysis?

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  • \$\begingroup\$ Maybe I'm missing something, but I don't see a heck of a lot of difference between the three, assuming a 4-layer board with power planes under the chip. C13 has a bit more resistance from the caps to the power planes so it might show less resonances. I'd be a lot more eager to believe the claims if the author could show empirically that one is significantly better than the other (with a TDR or whatever). \$\endgroup\$ – Spehro Pefhany Jul 31 '14 at 13:02
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The EMC right approach is C19 because the high-frequency ripple which is generated from the IC is routed over the C19 pads and therefore it is filtered.

Keep the resonance frequency in mind. If noise is generated at >300MHz a "classic" 100nF 0603 (1608 Metric) X7R capacitor is too big because its resonance frequency is at about 20MHz and on frequencies bigger than that it starts to work like an inductor. A capacitor with 1nF or 100pF would be needed here.

To simulate that you can us REDEXPERT or SimSurfing. The size and the voltage rating of the capacitor plays a big role too.

There are two aspects:

  • Reduction of the noise and high-frequency ripple
  • Power delivery for the IC

The result of those two considerations is to use multiple capacitors in different technologies:

  1. A few hundred pF to a few nF (e.g. 100pF to 3.3nF in 0402 or 0603) as close as possible in the C19 way (route from the IC to the capacitor and then go down to planes with vias)
  2. A bigger ceramic cap with a few hundred nF (100nF - 1uF)
  3. A tantalum cap with a few uF

This is my approach to reduce EMC.

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The critical thing here is how you think about the layout. C19 will indeed keep high frequency from the chip from getting into the rails, and vice versa, but you're not trying to filter high frequency noise (at least usually), you're trying to minimize the impedance across the power rails from the perspective of the IC.

Effectively, C13 has the capacitor and the power rails in parallel across the chip's power connections. C19 has them in series, and C18 is a mix of the two.

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    \$\begingroup\$ The capacitor and the power planes are electrically in parallel in all three cases. The only difference is the relative locations of the parasitic inductances of the vias and the traces. \$\endgroup\$ – Dave Tweed Jul 31 '14 at 11:17
  • \$\begingroup\$ I think I can see how this layout decreases the impedance of the traces, and the inductance of the vias might actually be beneficial here as the supply voltage would overshoot after a period of high current draw, recharging the capacitors faster. However, this also means that this overshoot would reach the IC first. I'm not sure what is preferable in practice. \$\endgroup\$ – Simon Richter Jul 31 '14 at 13:47

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