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Why modern CPU vendors prefers increasing the maximum length of the pipeline over increasing the clock?

Accordingly my understanding, increasing either increases the number of gate switches and so increases the energy dissipation.

So if both provide the same effect, how one is better than another?

Increasing the pipeline even has a disadvantage: it may be hard to use the full pipeline length in all components of a CPU, so it is wasted.

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    \$\begingroup\$ What makes you think long pipelines are prefered? The P4 had a VERY long pipeline and while it showed marginal benefit for media decoding (which has lots of steps...) it was rubbish for everything else. The Core2 arch significantly shrunk the pipeline.. What would you class as a long pipeline and a short? \$\endgroup\$ – JonRB Jul 31 '14 at 12:45
  • \$\begingroup\$ @Naib: But why don't we shrink the pipeline even more and instead increase the clock making a 10GHz CPU? \$\endgroup\$ – porton Jul 31 '14 at 12:48
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    \$\begingroup\$ longer pipeline == more stages == each stage can be constructed using few transistors. Fewer transitors makes it easier to run at higher clock rates. This was done during hte cpu clockrate races... that isn't the case anymore as its more a CPU core race.. In short MARKETING. more GHz == BETTER from marketing, rather than more capability == BETTER \$\endgroup\$ – JonRB Jul 31 '14 at 12:51
  • \$\begingroup\$ @Naib except that it is not so much 'fewer transistors' but 'fewer transistors in the critical path' (the stages can be very wide but must not be too deep) you should make your comment an answer. \$\endgroup\$ – Wouter van Ooijen Jul 31 '14 at 13:07
  • \$\begingroup\$ See electronics.stackexchange.com/questions/81344/… \$\endgroup\$ – pjc50 Jul 31 '14 at 13:13
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That's because there is a limit to the clock frequency but not to the pipeline length.

When you make a digital circuit the maximum clock frequency is determined by the so called "critical path": you have a clocked register, some combinational logic and another clocked register. If your clock period is shorter than the time required from the combinational logic to output a valid result then you have a problem. This requirement must be met for each possible input, so in the logic there usually is a longer path, the critical path, that is the most time consuming one. Have a look here:

schematic

simulate this circuit – Schematic created using CircuitLab

Note that I omitted the clock signal for clarity (and laziness).

Assuming that each nand and each nor have the same propagation delay \$t_D\$, while the AND1 is built with two nand having a propagation delay of \$2t_D\$ you can see that the longest path is from REG1 (or REG2) to REG4 through AND1 and NOR2, the total delay being \$T_{D_{max}}=3t_D\$. Your clock can't be faster than this, so that $$f_{CK}\leq\frac{1}{T_{D_{max}}}$$

Now imagine a 64bit floating point multiplier. That can have a critical path that is way, way longer than this. What can we do about that?

  1. Keep a low clock frequency, saving power and relaxing the constraints on some other, non critical transistors
  2. Break the critical path with another D flip flop

The second option would make the longest path shorter, thus allowing higher clock frequencies.

You might say well then, why don't they just make shorter critical paths rising the clock frequency? That's because transistors work well till a certain frequency that can not be exceeded, after that you can't increas clock frequency anymore but you can add pipeline stages to make more computations per clock cycle. Moreover, distributing a faster clock is way more difficult than a somewhat lower one, and the compilers nowadays can make a very, very smart use of the pipeline to don't waste any clock cycle.

I'd add that a modern superscalar processor such as the one heating the enviroment in your (and my) pc is way, way more complicated than a "pipeline vs frequency" battle. I suggest this site, there are some white papers and quite a number of talks about a new architecture, so the guy makes a lot of comparisons with a modern CPU. And a plus: the speaker is Gandalf.

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  • \$\begingroup\$ Above it was said that P4 had very long pipeline. Isn't shortening this pipeline two times capable to turn a 4GHz CPU into a 8GHz CPU? I yet don't understand. \$\endgroup\$ – porton Jul 31 '14 at 13:49
  • \$\begingroup\$ Theoretically one can time a pipeline stage shorter than the worst case for the logic depth. As with any speculation, this requires the means to detect and recover from incorrect speculation. I suspect design complexity, difficulty of validating/testing, poor tradeoffs in area/power for modest frequency increase, and perhaps other factors prevent such from being implemented. \$\endgroup\$ – Paul A. Clayton Jul 31 '14 at 13:50
  • \$\begingroup\$ That nails it. Moreover keep in mind that shortening the pipeline = adding flip flops, that may or may not be convenient regarding area and $$$. \$\endgroup\$ – Vladimir Cravero Jul 31 '14 at 13:51
  • \$\begingroup\$ @porton The frequency is the reciprocal of the time spent in a pipeline stage. For a given amount of work (on the critical path) to handle an instruction, dividing that work into more stages allows each stage to be shorter, which increases the frequency. Halving the depth of the pipeline could halve the frequency (there is more lost time in a longer pipeline, so halving depth would not halve frequency). Think of an assembly line where each clock tick the work item is passed to the next worker. Adding workers means each worker does less work allowing a shorter tick. \$\endgroup\$ – Paul A. Clayton Jul 31 '14 at 14:01
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Actually, the division of the CPU into multiple stages and the pipelining of such stages is what ALLOWS for higher clock speeds. If instead of multiple stages the whole CPU was composed of a single stage where the signal must propagate from the start to the finish in one go, this very long path would mean that the clock limit would be much lower. If your CPU was made of a single path that took 90ns to travel, your CPU would be limited to 10mhz or so, even if made out of very small transistors. But, the same system, made out of nine 10ns steps can run at 100mhz or more, and so on.

So, dividing the CPU in stages and pipelining such stages is what makes modern CPUs able to reach higher clock rates and the way those stages are designed will decide the max path length, resulting in the maximum delay and this max delay will say whats the max clock of the resulting CPU archtecture.

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