Procedural blocks in verilog

Question

We have two types of procedural blocks in verilog: initial and always block. The statements inside these blocks are executed sequentially. Does that affect the timing of these signals? For example, in the code below:

initial begin
  a = 1'b0;
  b = 1'b1;
end

Will the assignment of b will take place a small time after the assignment of a? If not what will be the difference between this and the concurrent blocks in verilog, i.e.,assign statements?

assign a = 1'b0;
assign b = 1'b1;

Answer 1

Does that affect the timing of these signals?

Not really.

Yes a&b are evaluated sequentially but in the same simulator timestep, not seqential in terms of electronic design.

initial begin
  a = 1'b0;
  b = 1'b1;
end

a and b are essentially evaluated in parallel. but your simulator can not do that, the only time that this needs careful consideration is if you rely on previous results.

The following are just examples and would imply latches in some case and should not be used in RTL like this.

always @(posedge clk) begin
  a = y;
  b = a; //this is b=y
end

is not the same as:

always @(posedge clk) begin
  b = a;     //This is old y
  a = y;
end

For clocked systems (implying flip-flops) we use non-blocking (<=) the following 2 examples are the same:

always @(posedge clk) begin
  a <= y;
  b <= a; //this is old y
end

always @(posedge clk) begin
  b <= a;     //This is old y
  a <= y;
end

Answer 2

initial begin
  a = 1'b0;
  b = 1'b1;
end

The initial block is a mechanism for describing how you want your signals to behave initially. When synthesised, the tools use these values as the initial vales for each register. The registers are not assigned these values sequentially, they have these values from the start.

In the case of simulation, the CPU processes the instructions given, one after the other

assign a = b;

As I mentioned in my comment, assigns are a synthesizable construct that essentially mean "connect this wire to this reg/wire". In reality, that assignment is going to end up optimised by the tools.

With all asynchronous assignments, the timing implications are going to depend on how long the wire is between 'a' and 'b'. If a mux is used, or any other processing performed (say, assign a = b + c), that will also have an inherent propagation delay. How long are these in reality? Probably much shorter than a clock cycle. However you must be careful when going mad with assign statements. For example, this may get you into trouble with your timing constraints.

assign OutputQLLParity = QLLDout[23:21]^
                        QLLDout[20:18]^
                        ...
                        QLLDout[5:3]^
                        QLLDout[2:0];

Heading on to always blocks.

always @(posedge clk) begin
  a <= y;
  b <= a;
end

Notice the clk in the sensitivity list. This means that this process is going to only be executed (for lack of a better word) on the positive edge of a clock.

Say, for example, that y changes after the clock rising edge. Even though y has changed, a is only going to be updated on the next rising edge.

A is not updated directly on the rising edge, it's updated a tiny bit after that (this is called delta time). So b will only change on the clock cycle after that, a clock cycle after a.

Here, a handy timing diagram for you:

          _____      _____      _____      _____
clk  ____/     \____/     \____/     \____/     \____
             ________________________________________
y    _______/       
                     ________________________________
a    _______________/       
                                _____________________
b    __________________________/       

So what does this look like in hardware?

They're not technically d-types in actuality, but it gives a good idea. A clocked register is used that propagates the input to the output on the rising clock edge.

^{simulate this circuit – Schematic created using CircuitLab}

Last note:

See the difference in assignments. = is a blocking assignment, <= is non-blocking.

It is possible to mix and match these in some cases, but if you're starting out with this, and just generally for your own sanity in the beginning, a good rule of thumb is = is for assigns, initial blocks and processes without sensitivity lists*. <= for processes with sensitivity lists.

* bit hazy about this. I don't use combinatorial processes in verilog very often.

Answer 3

The example which you have taken is of blocking statements.
Yes, initial & always blocks are sequential whereas assign statements are concurrent.
In the initial & always block a=1'b0 will be assigned before b=1'b1 is assigned. Whereas in the case of assign statements, a & b will be assigned concurrently.

In the case of non-blocking statements "<=", if the value assigned to a depends on b then a will be assigned first, then b. But since a value depends on b, the value of a is modified after that. This is called discrete event simulation