# State Machine w/ Decoder

I'm trying to design a State Machine that acts as a synchronous lock. There is only 1 input (X) and one output (Lock= 0, Unlock = 5v). The machine will only unlock if the following order is put in: 0* 1* 1* 0* 1* 1* 0. (An asterisk means I then push the clock button. So it should switch to unlocked after just changing the input from 1 to 0) Only this combination should unlock it. A reset button should also be included.

My professor gave us the State Table and Diagram for the project. I have tried to implement it using JK and D flip flops, to no avail.

A classmate said to try using a 4x16 Decoder, with active low output, to do the project. He said to NAND the 0 outputs, and use D Flip Flops.So I put a NAND to the zeroes of each Next State, and connect it to the D Flip Flops, right?

Also, how then do I get my output? Do I AND the 3 D Outputs (Qa Qb and Qc) as well as my X Input?

Additional information: We use TTL (0 and 5v only) and I have to design this out on a hardware trainer.

• Your description is a bit confusing, can you draw a schematic? Also, what parts are you using? They sound like TI chips. Aug 1, 2014 at 17:38
• I find the question clear enough, plus implementing a sequence detector is quite a common learning project. hint instead of attacking the problem with the usual karnaugh map thing try an euristic approach: how would you do that with a piece of paper? Aug 1, 2014 at 18:18
• Fun, I can think of one or two ways. (But probably there's some clever approach...) Why don't you first try and do something that will distinguish 0*1 from 1*1, 0*0 and 1*0, and work your way up from there. Aug 1, 2014 at 18:18

What you are designing is basically a sequence detector.What you need to do is set up 8 states, each of which representing the current state the circuit might be in, and the draw a state transition table ( table showing how every current state maps to a next state ), then extract the sequential circuit that will be needed to implement the circuit.

A document explaining in detail how to design such a circuit can be seen HERE.

Operated in the way you describe, this works, and the switches are normally-open momentary SPST, except for the toggle, which is SPDT ON-NONE-ON.

The circuit doesn't have one input, it has three: Reset/Clear, data, and clock, and one output, unlock bar. When you build it, make sure you debounce the clock and - if you want a positive true output - invert the output of U5.

Looking at it again, you could pull U1A-D up to +5 with 10K and then make a SPST switch to pull U1A-D down to GND for a zero or break the switch for a 1 at U1A-D.

• This seems a very straightforward approach, however since the first bit required to be entered is a 0, I would run the reset button to the preset pins, otherwise entering the first bit in the sequence would be unnecessary.
– Tut
Aug 3, 2014 at 0:00

It would be good to note that this relation could probably be reduced using a kmap - ie, you probably dont need all 8 states for this. Might save you some hardware debugging(fewer 'moving' parts) if you attack this on paper first.