I'm a beginner to FPGA programming. I just started programming an Atlys Spartan 6 board and so far have written one program to blink LEDs in a counter pattern.
Now I'm trying to send the clock signal down-sampled to audio frequencies to the AC97 codec. Here is the Verilog program I've written:
module music( input clk, output ac97_sdo ); reg [25:0] count_aud; reg clk_aud; assign ac97_sdo = clk_aud; /* down-sample the 100MHz system clock to 1kHz */ always @(posedge clk) begin count_aud <= count_aud + 1; if (50000 == count_aud) begin clk_aud <= !clk_aud; count_aud <= 0; end end endmodule
The bit-file generation is fine, but the code doesn't seem to work - I don't hear anything either on Line Out or on HP Out (I don't know how to control the output, either), and I don't have enough experience with the AC97 specification to figure this out. The audio part of the UCF is:
NET ac97_bitclk LOC = L13; NET ac97_sdi LOC = T18; NET ac97_sdo LOC = N16; NET ac97_sync LOC = U17; NET ac97_reset LOC = T17;
Do I need to use the bit clock, sync, reset, etc. to make this work? If yes, how can I go about it?
I couldn't find any detailed information on the Atlys Reference Manual.