Verilog assigning wire by iterating over array

How to assign a wire with a AND operation of a wire array?

    parameter row = 4;
parameter col = 8;


logically i want to do

For a mutlibit wire the reduction operator & can be used:

wire [row-1:0] ready;


However this will not work with unpacked arrays (multi-dimensions).

One solution is to create a loop to index the dimensions ANDing the values with the result so far. This could be achieved with some thing along the lines of:

output reg allready;

always @* begin