Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors).
My answer to this is that we should introduce a buffer between the clock and the second flop such that:
Tnet + Tc-to-q - Tskew <= Tclk
where Tnet=delay of the combinational circuit Tc-to-q= flip flop delay Tskew = difference in clock arrival timings at the two flops
Is there a better answer? Thanks in advance.