Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors).

My answer to this is that we should introduce a buffer between the clock and the second flop such that:

Tnet + Tc-to-q - Tskew <= Tclk

where Tnet=delay of the combinational circuit Tc-to-q= flip flop delay Tskew = difference in clock arrival timings at the two flops

Is there a better answer? Thanks in advance.


Delaying the clock of the following register would steal time from the next stage in the pipeline, imperiling the setup time of the register following that.

If you know for a fact that the next stage has a sufficiently short propagation delay it could work, but it would be cause for a lot of caution and explicit warnings in the design documents, less someone later revise that next stage on the assumption that they have a normal clock interval to work with.

A more traditional / textbook answer would be to add an additional pipeline stage by inserting a register somewhere in the middle of the long combinatorial path, breaking it up into two paths each of which will meet timing (or, in an extreme case, inserting multiple registers).


By slowing down the clock Tclk > Tc2q+Tsu+Tcomb

so If we increase the period then without breaking the combinational delay it works but at the cost of decrease in frequency


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