I have an application where I want to multiply from a xtal oscillator at 32KHz to a system clock of 40MHz. A standard PLL isn't going to do the job, because the 32KHz jitter is measured in ns. Since the PLL multiplies up the phase noise, and the output period is much shorter, the output will get swamped in noise from the reference - even if the PLL adds no noise at all.
I saw a few patents and designs kicking about which are for a frequency locked loop, and the claim is made several times that these designs are insensitive to input jitter, presumably because they use input counters rather than the more traditional PFD of the PLL.
Can anyone explain to me how a FLL would reject input jitter without having the reference divided down by some big integer? If that is done, then the feedback also needs a big divide ratio and VCO noise at the FLL output will rise (due to very low correction frequency). Ideally I would like the reference divided by unity and the feedback by 125, output frequency can be a few % off if necessary, its just a micro system clock.