I have an application where I want to multiply from a xtal oscillator at 32KHz to a system clock of 40MHz. A standard PLL isn't going to do the job, because the 32KHz jitter is measured in ns. Since the PLL multiplies up the phase noise, and the output period is much shorter, the output will get swamped in noise from the reference - even if the PLL adds no noise at all.

I saw a few patents and designs kicking about which are for a frequency locked loop, and the claim is made several times that these designs are insensitive to input jitter, presumably because they use input counters rather than the more traditional PFD of the PLL.

Can anyone explain to me how a FLL would reject input jitter without having the reference divided down by some big integer? If that is done, then the feedback also needs a big divide ratio and VCO noise at the FLL output will rise (due to very low correction frequency). Ideally I would like the reference divided by unity and the feedback by 125, output frequency can be a few % off if necessary, its just a micro system clock.

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    \$\begingroup\$ If the PLL output drives the VCO then more filtering on the input to the VCO will produce lower jitter assuming that the jitter you have on your LF oscillator does not have components that are too low in frequency. \$\endgroup\$ – Andy aka Aug 6 '14 at 14:14
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    \$\begingroup\$ This doesn't go to your question, but is there a reason you can't just use a separate oscillator? US$1.35 for a CMOS output in quants of 1, probably lower cost, less real estate, and less jitter than the solution you're looking at now. In fact, you could divide that 40MHz clock by 1250 to give you your 32KHz with low jitter -- digikey.com/product-detail/en/KC2520B40.0000C10E00/… \$\endgroup\$ – Scott Seidman Aug 6 '14 at 14:49
  • \$\begingroup\$ Feedback needs to be 1250. 40 MHz / 125 = 320 kHz. Furthermore, if your VCO is stable you can always filter out phase noise from the PD (as Andy aka stated). You just put a bigger time constant on your loop filter. Finally, if you had 1 nsec jitter on your 40 MHz clock, what would that hurt? And finally finally, why does your 40 MHz need to be synchronous with the 32 kHz? If it doesn't, it will be cheaper and take less space to just add a 40 Mhz XO. \$\endgroup\$ – WhatRoughBeast Aug 6 '14 at 14:52
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    \$\begingroup\$ To put Andy's comment another way, it's not correct that "the PLL multiplies up the phase noise". Typically a PLL will have a jitter transfer response spectrum. Very low frequency jitter (or wander) will indeed be passed through on a ns-for-ns basis, meaning the phase error will be greater on the higher-frequency output. But high frequency jitter can be dramatically attenuated. What is "high frequency" all depends on the loop filter characteristics. \$\endgroup\$ – The Photon Aug 6 '14 at 16:07
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    \$\begingroup\$ And if you want your 40 MHz clock to be in sync with your 32 kHz clock, then you should want the 40 MHz clock to drift when the 32 kHz one does. If you don't want the 40 MHz clock to be in sync, then just add a separate oscillator like other comments suggested. \$\endgroup\$ – The Photon Aug 6 '14 at 16:09

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