Sorry to have to be contradictory here, but I must say yes - you can use other tools, or at least work around the bloated parts. Simulation and logic synthesis are in fact separate targets. However, you're much more limited when it comes to bitstream generation. There have been a few tools, like Jbits, but for the most part you're restricted to vendor supported tools. Xilinx tools for this are XST (Xilinx Synthesis Technology), par (place and route) then bitgen (to make the bit file). They are what ISE uses as its backend, so you get them in WebPack.
For a workable toolchain, it's often much quicker to enter your designs in Emacs, simulate them with Verilator, Icarus Verilog or GHDL, inspect simulation results with gtkwave.. and finally, synthesize to logic with XST etc. XST can be run without using ISE, but it's a somewhat more complicated procedure you'll want to use make for. Check the ISE user guides; XST manual chapter Command Line Mode, and the Command Line Tools chapters on PAR and BitGen. If you want post-synthesis simulation, that's also technology (and thus vendor) specific.
As a rule, you can write all your logic without vendor specific instantiations (the ISE snippets show examples which infer usage correctly), but the DCMs can't be described that way. You'll thus have to make your simulation benches without them, which shouldn't be hard as you can just add the required clocks there.