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I'm struggling with WebPack's bloat and random broken pieces when running in Linux. So, I'm thinking it may just be easier to use a different compiler/simulator.

Is it possible to use something different? Note, all I need to do is get a .bit file. I have the Butterfly One which has an external programming application. (which only requires a .bit file)

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No. Only the vendor's tools produce .bit. But you can use many for simulation. You may just need a Xilinx library for it.

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  • \$\begingroup\$ Ah :( Is that because the internal structures of FPGAs and thus .bit files are usually trade secret? \$\endgroup\$ – Earlz Apr 1 '11 at 23:33
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    \$\begingroup\$ @earlz Yes, the binary format is a secret. \$\endgroup\$ – Philippe Apr 4 '11 at 13:14
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Sorry to have to be contradictory here, but I must say yes - you can use other tools, or at least work around the bloated parts. Simulation and logic synthesis are in fact separate targets. However, you're much more limited when it comes to bitstream generation. There have been a few tools, like Jbits, but for the most part you're restricted to vendor supported tools. Xilinx tools for this are XST (Xilinx Synthesis Technology), par (place and route) then bitgen (to make the bit file). They are what ISE uses as its backend, so you get them in WebPack.

For a workable toolchain, it's often much quicker to enter your designs in Emacs, simulate them with Verilator, Icarus Verilog or GHDL, inspect simulation results with gtkwave.. and finally, synthesize to logic with XST etc. XST can be run without using ISE, but it's a somewhat more complicated procedure you'll want to use make for. Check the ISE user guides; XST manual chapter Command Line Mode, and the Command Line Tools chapters on PAR and BitGen. If you want post-synthesis simulation, that's also technology (and thus vendor) specific.

As a rule, you can write all your logic without vendor specific instantiations (the ISE snippets show examples which infer usage correctly), but the DCMs can't be described that way. You'll thus have to make your simulation benches without them, which shouldn't be hard as you can just add the required clocks there.

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    \$\begingroup\$ GHDL will simulate most Xilinx unisim and simprims entities just fine. Look for the VHDL source code in the Xilinx ISE install tree. \$\endgroup\$ – wjl Jul 26 '11 at 18:43
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There is an alternative to installing and running the Xilinx tools yourself. Plunify.com offers these tools "in the cloud". It might be easier to operate the tools through the Plunify interface.

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  • \$\begingroup\$ That's neat. I may use that instead, but I'll need to evaluate it a bit more first \$\endgroup\$ – Earlz Apr 4 '11 at 22:09
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Here is an example for an IP STACK, written in VHDL. Is simulated, RTL and net-list post NGD: http://bknpk.ddns.net/my_web/IP_STACK/start_1.html

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  • \$\begingroup\$ It would be better to say more here. \$\endgroup\$ – Brian Carlton Dec 27 '14 at 17:38
  • \$\begingroup\$ Link-only answers are discouraged in case the information at the link is later lost. Please summarize the information at the link. \$\endgroup\$ – Null Dec 27 '14 at 17:58

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