Is there a more optimized way of making an incrementer than a full adder?

Question

I'm designing a very simplistic microprocessor as a project to help learn VHDL. So I'm needing something to increment the 8 bit program counter. I will need to increment it by two. Is there a better (either faster or less logic required for equal speed) design than using an 8 bit full adder? I'm also interested for the same thing for if you only needed to increment the PC by 1.

Answer 1

Hmmm, this all depends on what exactly you are trying to learn. A counter or adder in VHDL is super easy:

  signal count  :std_logic_vector (7 downto 0) := (others=>'0');
  . . .
  process (clk)
  begin
    if rising_edge(clk) then
      if count_enable='1' then
        count <= count + 1;  -- could be +2 also
      end if;
    end if;
  end process;

And that's it! The VHDL compiler will normally synthesize a full-adder for this, and them optimize out everything that isn't needed-- ending up with some sort of half-adder. The nice thing about doing it this way is that your code is readable and easily understood and the compiler deals with figuring out the best way to implement it.

Now, if you are trying to learn about adders and counters and such then my little code snippet isn't going to help you much. In that case you should implement a half-adder the manual and hard way.

Answer 2

You don't actually need a full adder for increment by 1; using half adders where the first input is set to 1, and carry bits are daisy chained to the next bit would do. I'm not sure if there's a still better way to do it, though.

Incrementing by two could be done by ignoring the first bit of a number, and using the same method above.

NOTE: not a VHDL expert, can't state if this could actually be faster, but should be less logic.

Edit: Also, there's an expired patent for a simple binary incrementer that might be of interest: http://www.freepatentsonline.com/3989940.pdf

Answer 3

Maybe you can use a binary counter built from JK flip-flops, one where you can load the bit value into each flip-flop, then just toggle the clock. Counting by 2 would mean loading everything but the least significant bit into the counter since that bit never changes.

This probably won't be better than a half-adder implementation, but perhaps it is easier to understand :)

Answer 4

What specifically you need is series of T-triggers + a bunch of AND gates. You should pass 'toggle' signal to bit n only if all previous bits were 1. This is much faster than full adder, does not require carry look ahead and eats way less transistors.

PS. Some time ago I was wondering exactly the same question ;-)

Answer 5

It certainly does seem as though there should be a simplification -- after all one of the inputs is limited to a fixed value that is the same every time!

Unfortunately, that's only enough to get a small reduction in number of gates, but not much of a reduction in time to complete. That is because you do get simpler adders -- they only have 1 input plus carry, so the base adders have about 1/3 fewer gates. But the delay is determined by the carries, which are not reduced, they still must ripple up the whole chain. So, you don't get much meaningful speedup. And, if you want to go fast, at least half the gates are dealing with the carries, so that 1/3 gain reduces to about 1/6 fewer gates overall. In the end, roughly the same speed, and 85% of the size of a full adder.