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According i.MX6 SMART DEVICE SYSTEM of freescale layout board, it uses 8 layers, my question is about the inner layers, they are striplines with a continuos GND plane in one side but in the other side they have a power layer that is broken A LOT of times (they make a lot of power islands), and some important signals cross those broken planes and that would mean a difference in Zo of the line, which mean reflections, so te integrity of the signal won't be optimal and when we are talking about RAM data lines and other kind of sensitive lines that's a big problem, so that thats my question, i mean that's the reference design, but in my opinion is against all theory, can some one tell me if i'm wrong or gimme an awnser to orientate me in this matter please.

This is a screenshot of the internal layer 2 and the power plane that makes the stripline, there you can see the SoC and the RAM lines. enter image description here

This is the stackup: enter image description here

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    \$\begingroup\$ What is the stackup? It's not optimal to have cuts in a reference plane. But, maybe the routing is much closer to the continuous GND plane than the broken power plane. And thus is't not a severe issue. Check the stackup. \$\endgroup\$ – Blup1980 Aug 12 '14 at 6:48
  • \$\begingroup\$ @Blup1980 There I added the stack up info, there is some difference between the tickness of the GND dialectric (4 mils) and the PWR plane tickness (4.5 mils) but I don't think that that is considered as "much". \$\endgroup\$ – JAMS88 Aug 12 '14 at 22:51
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You can route across a cut up plane with no issues as long as each cut up plane is paired with a tightly coupled solid (gnd) plane -and- you engineer the PDN (bypass network) to have sufficiently low impedance between all power plane islands and ground (use something like my PDNtool.com for this).

If you make the cuts wider than about 1/3 the electrical length of the rise/fall time of your signals, you will start to see some reflections due to the lower capacitance. This can easily be simulated if you have access to an IBIS simulator.

Also the plane nearest to your stripline traces will "dominate", so if that is solid you have no issues either.

PS: Reference boards are not holy. There are MANY reference boards out there with lots of serious design errors. So watch out!

Does that answer your question?

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    \$\begingroup\$ +1 for reference designs not being holy. Often they're just "here, we just got it to work", not "here is how we think it should be done after exhaustive testing". This is particularly true for new parts. \$\endgroup\$ – Connor Wolf Aug 12 '14 at 8:30

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