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What the circuit is designed to do

The following circuit is designed to accept a rectified (low frequency) sinewave input of amplitude 0-30V, and filter it through charging a capacitor until its voltage reaches a certain value settable via P1. I want the capacitor to be regulated between [7V;12V] when that happens. I thought that circuit would follow the input when not tripped, and oscillate around 12V (for example) when tripped. I was wrong.

Edit: To make it clearer, I am just trying to rectify a low frequency sinewave and make sure it's high enough to generate 5V. However the amplitude may be higher than the breakdown voltage of the capacitor, hence this protection circuit.

Capacitor voltage limiter

What the circuit does instead

To test the circuit, I've injected DC and increased the voltage until the protection tripped - set arbitrarily at 7V in my test. I was expecting the voltage of the capacitor to be saturated at 7V and stay there, but instead it leaked out quickly (a few seconds) down to ~1.5V and counting. I shut down the power supply and restarted the process, and the capacitor did the exact same thing: follow, then drop.

What's wrong?

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  • \$\begingroup\$ Do you have a load attached? What current does it draw? \$\endgroup\$ – The Photon Aug 12 '14 at 19:15
  • \$\begingroup\$ How long does it take the voltage to drop after the circuit is tripped? 1 minute? 1 microsecond? \$\endgroup\$ – The Photon Aug 12 '14 at 19:17
  • \$\begingroup\$ A few seconds tops. \$\endgroup\$ – Mister Mystère Aug 12 '14 at 22:10
  • \$\begingroup\$ Are you sure this circuit isn't meant to be built with Q1 as an NFET and Q2 as a PFET? \$\endgroup\$ – The Photon Aug 12 '14 at 22:15
  • \$\begingroup\$ Honestly I'm not sure anymore, what do you think? \$\endgroup\$ – Mister Mystère Aug 12 '14 at 22:18
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As drawn, your circuit should be able to hold it's output voltage for several seconds.

The potentiometer P1 does provide a leakage path though, with a time constant of about 50 s. This means you'll see the voltage droop noticeably in just a second or two. It should take about 2 min to get down to 1.5 V, though.

Once it drops far enough, Q1 should be disabled, causing the voltage to rise again. This cycle would continue, resulting in an oscillating output voltage. If you're measuring the output with a multimeter, it's possible this is happening (but much faster than expected) and you're just seeing the average value of the oscillating voltage, rather than the value from any particular instant in time.

If you have any load attached to the terminals on the right, that will also speed up discharging the capacitor.

Another possibility, if you wired the capacitor in reverse, there would be substantial leakage current through the capacitor itself. I'm saying this because at 1 mF, you're almost certainly using either an aluminum or tantalum electrolytic (or a bunch of them in parallel, in which case it would only take one wired wrong to mess things up).

Edit: Also look at the leakage current spec on your capacitor. Looking at a few different 1 mF parts, it's quite easy to find one with leakage current equal to or larger than the drain you're allowing through P1.

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  • \$\begingroup\$ Thanks for your answer. It definitely does not take more than a few seconds to get down to 1.5V... And the capacitor (only one) is wired correctly. I've got no other load. If the capacitor is supposed to take a minute to discharge significantly, how can there be oscillations fast enough for my multimeter to average them? I'm not concerned about the speed at which it leaks out, but rather why the regulation is not done. \$\endgroup\$ – Mister Mystère Aug 12 '14 at 22:22
  • \$\begingroup\$ Regardless of the speed at which the capacitor is discharged/leaking, Q2 should close again when the voltage gets low enough under the tripping point right? Is your edit explaining why it doesn't (I didn't quite get it)? \$\endgroup\$ – Mister Mystère Aug 26 '14 at 10:45
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Look at Q2 - the parasitic diode just takes all the charge away unless you keep the input voltage at a high enough level to keep that diode from being forward biased. BTW, there is no such thing as "pure DC".

Try sticking a diode in series with Q2 but somehow this is probably messing with what you are trying to achieve (which you haven't completely come clean about).

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  • \$\begingroup\$ The Q2 body diode won't drain the output capacitor if he keeps the input voltage high. Which is what I think he is asking about. \$\endgroup\$ – The Photon Aug 12 '14 at 19:29
  • \$\begingroup\$ @ThePhoton - it's his test with DC I'm making a critique over. If he uses a rectified input then the diodes will be reverse biased and not form a discharge path however, when he turns the dc power off there's likely to be a fairly robust discharge path - I can't see another explanation 'cept maybe it's wired up crap. \$\endgroup\$ – Andy aka Aug 12 '14 at 20:12
  • \$\begingroup\$ My reading is he saw the voltage droop, then he turned off the input supply. But it's certainly possible he did it the other way. My bet is on an electrolytic capacitor wired in reverse. \$\endgroup\$ – The Photon Aug 12 '14 at 21:58
  • \$\begingroup\$ Thanks Andy, you will recognise the circuit you've suggested the last time I posted here. I'm more concerned about the absence of regulation than the rather important leakage, but you've got a point about the parasitic diode. However here the capacitor was discharging even when the input was 10V above the capacitor voltage... As for "pure DC", of course, it was only to say it wasn't a rectified wave. \$\endgroup\$ – Mister Mystère Aug 12 '14 at 22:28
  • \$\begingroup\$ @Andyaka, what do you think of The Photon's comment of my question about the fact Q1 should probably be a NMOS? \$\endgroup\$ – Mister Mystère Aug 12 '14 at 22:31

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