Latency: Flash memory is slower than the CPU.
So, if you need to run the CPU at full speed (which is optional, because lower speed saves power), then the number of wait states need to be programmed. IIRC, the CPU can run without any wait states at 24MHz or below. Running at those lower speeds will save significant power in a low power application, which still running with good performance.
"on-the-fly": the CPU can adjust the clock speed while it is running.
Hence, to get the best throughput vs power, it might run at a low-clock speed to save power, while still doing work, then when needed, crank up the clock, when flash will need more wait cycles to work reliably.
Cache: the prefetch buffer is a simple type of cache.
The internal flash memory is 64 bits wide. The pre-fetch buffer is the same width, so it can hold upto 4 instructions in each of its two blocks. AFAIK it is least recently used, and hence just cycles. I imagine having two blocks simplifies the circuitry, and avoids contention between program load and instruction decode.
Half cycle: This only applies when the CPU is running at less than 8MHz
The programmers manual says:
Half cycle configuration is not available in combination with a
prescaler on the AHB. The system clock (SYSCLK) should be equal to the
HCLK clock. This feature can therefore be used only with a
low-frequency clock of 8 MHz or less.
The flash memory subsystem is fast enough to be read in half a clock cycle. That might allow the chip to optimise power use, or avoid contention between DMA or the CPU, read two instruction blocks, or maybe something else. I don't know what it actually does, and I can't remember reading about it in the manuals. I apologise for speculating; maybe a web search or query on ST's forum might find a better answer.