Today I ran out of gates on my Xylinx Spartan 3 (Basys2 by Digilent) FPGA.
This was not a surprise to me as I had implemented an 8 bit x 2048 array for use as an FIFO buffer.
type MEMORY is array(0 to (MEM_L - 1)) of std_logic_vector(7 downto 0);
MEM_L is an integer, value 2048.
I read through the product brief, and as I understand it there is 72 kB of bi-directional RAM on Spartan 3E series FPGA's.
However I do not know how to use it (program it) using VHDL. How would I go about declaring that I want some data to be stored in RAM memory?
Initially I assumed the use of RAM was up to the compiler (synthesizer and implementer tools) and that I was not able to control how it was used directly, however I suspect that I was wrong in this assumption, because the implementation process failed due to my FIFO being too large for the number of gates supported. (Approx 100 k gates.)
I should add that I wasn't able to find an answer through google, perhaps I didn't know quite what to search for?
EDIT: That should have said 78 kb of ram, 78000 bits.