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Below is my understanding of how NAND flash memory is organized, with this design it should be possible to just erase a single page and program it instead of erasing an entire block. My question is, why don't NAND implementation erase at a more granular page level? Intuitively, all that needs to be done is to present the word line representing the page being erased, with a high voltage to remove electrons off of the floating gate while leaving the other word lines untouched. Any explanation about the reasoning behind this is appreciated.

NAND flash block organization

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If you don't wipe them all at the same time, you'll need a much higher voltage because you're trying to raise the floating gate voltage a certain voltage above the source voltage. If the source isn't tied to ground through the other transistors, many of the source voltages will already be at some level higher than ground. Furthermore, if you tried to use a higher voltage, some of that voltage would likely end up on some transistors with their sources tied to ground which may be enough to damage the transistor.

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  • \$\begingroup\$ Thanks a lot, that's a great answer. So I'm guessing for NOR then it should be possible to erase just all FGT on a particular word line, instead of all in a block? \$\endgroup\$ – Joel Fernandes Aug 15 '14 at 16:56
  • \$\begingroup\$ *since all the sources are grounded \$\endgroup\$ – Joel Fernandes Aug 15 '14 at 17:05
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    \$\begingroup\$ @JoelFernandes Although you technically could design a NOR flash to be capable of individual cell erasure, that's not done in practice. Because it requires a high negative voltage, not a 0 or a 1, to erase a cell, they link many cells up into blocks to perform this erase operation. In that way, your programming and read circuitry doesn't have to be capable of handling a large negative voltage. Since speed is so important in memory, this is a wise engineering decision. \$\endgroup\$ – horta Aug 15 '14 at 17:34
  • \$\begingroup\$ so -ve voltage is used to erase a cell? I thought for both NAND and NOR, a high positive voltage was used across gate/source to quantum-tunnel out the stored charge (thus setting it to a 1). Looks like I'm missing something. Also any good reference to literature for NAND/NOR circuitry organization would be appreciated. \$\endgroup\$ – Joel Fernandes Aug 15 '14 at 20:36
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    \$\begingroup\$ @JoelFernandes en.wikipedia.org/wiki/Flash_memory#NOR_flash It's a high negative voltage that pushes/tunnels the electrons out of the FG back to the source. That page also has a lot of references/links. To program, you apply a positive voltage and you get electrons stuck in the floating gate from the source/drain. The electrons would cause a negative voltage to occur above the channel forcing the channel to stop conducting, i.e. a 0. To reset back to a 1, you reverse the voltage to a really high level causing electron tunneling from the FG back to the source. \$\endgroup\$ – horta Aug 15 '14 at 20:58
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I was so confused by the idea of block erasing... I found a book explaining Flash memory in detail. You may be interested in the author's explantion:

...Erasing Flash in smaller chunks made management of code and data storage easier and safer. Most wonder why block sizes aren ’ t reduced all the way to the ideal of single byte/word erase. The reason is that the smaller the block, the larger the penalty in transistors and die area, which increases costs. While smaller blocks are easier to use and faster to erase, they are more costly in terms of die size, so every blocking scheme must balance its block sizes with device cost and the needs of its target application..."

cited from Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using Flash Memory Devices (IEEE Press Series on Microelectronic Systems) Joe Brewer, Manzur Gill

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