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Hello this will be an experts questions :) You should be familiar with the following topics

  • Xilinx Multi-Gigabit-Transceivers (MGTs), especially the 7-Series GTX/GTH transceivers (GTXE2_CHANNEL)
  • Serial-ATA Gen1, Gen2 and Gen3, especially Out-of-Band (OOB) communication

Question:

How should a GTXE2 be configured for Serial-ATA?

OOB signaling is not working neither RX_ElectricalIdle nor ComInit.

Introduction:

I implemented a SATA controller for my final bachelor project, which supports multiple vendor/device platforms (Xilinx Virtex-5, Altera Stratix II, Altera Stratix IV). Now it's time to port this controller to the next device family: Xilinx 7-Series devices, by name a Kintex-7 on a KC705 board.

The SATA controller has a additional abstraction layer in the physical layer, which is based on SAPIS and PIPE 3.0. So to port the SATA controller to a new device family, I have only to write a new transceiver wrapper for a GTXE2 MGT.

As of Xilinx's CoreGenerator doesn't support the SATA protocols in the CoreGen wizard, I started a transceiver project from scratch and applied all necessary settings as far as they are asked by the wizard. After that I copied the GTXE2_COMMON instantiation into my wrapper module, ordered the generics and ports into a meaning full schema.

As a third step I connected all unconnected ports (the wizards doesn't assign all values !!) to their default values (the default from UG476 or zero if not defined).

In step 4 I checked all generics and ports again against the UG476 if they are compatible to the SATA settings. After that I connected my wrapper ports to the MGT and inserted cross-clock modules if necessary.

As of the KC705 board has no 150 MHz reference clock, I program the Si570 to supply this clock as "ProgUser_Clock" after each board "bootup". The MGT is in powerdown mode (P2) while this reconfiguration. When the Si570 is stable, the MGT is powered up, the used Channel PLL (CPLL) locks after ca. 6180 clock cycles. This CPLL_Locked events releases the GTX_TX|RX_Reset wires, which cause a GTX_TX|RX_ResetDone event after additional 270|1760 cycles (all cycles @ 150 MHz -> 6,6 ns).

This behavior can be seen in chipscope, captured with a stable, uninterrupted auxiliary clock (200 MHz, slightly oversampled).

So the GXTE2 seams to be powered-up, operational and all clocks are stable.

GTXE2 ports to control the OOB signaling:

The MGT has several ports for OOB signaling. On TX these are:

  • TX_ElectricalIdle - forces TX into electrical idle condition
  • TX_ComInit - send a ComInit sequence
  • TX_ComWake - send a ComWake sequence
  • TX_ComFinish - sequence was send -> ready for next command

On RX:

  • RX_ElectricalIdle - RX_n/TX_p are in electrical idle condition (low-level interface)
  • RX_ComInit_Detected - a complete ComInit sequence was send
  • RX_ComWake_Detected - a complete ComWake sequence was send

Detailed error desciption:

  1. TX sends no OOB sequences if TX_ComInit is high for one cycle.
  2. RX_ElectricalIdle is always high

Tests:

  1. SATA loopback cable: cut a SATA cable and solder the apropriate wires ;) -- I'm using a special SFP to SATA adapter, which extends the KC705 with a SATA connector - http://shop.trioflex.ee/product.php?id_product=73
  2. SMA loopback cables: I moved the MGT and connected the LVDS wires to the SMA jacks and installed 2 SMA cables as cross-over.
  3. I programmed my old ML505 (Virtex-5) with onboard SATA connector to send ComInit sequences. The 2 boards are connected with a special SATA cross-over cable.
  4. I connected a HDD with a partial stripped SATA cable to the KC705 (SFP2SATA adapter) and connected a 2.5 GSps scope (yes the signals are undersampled, but it's good to see bursts and idle periods...).

Experiences:

  • Test 3 shows transmitted OOB sequences from Virtex-5 to Kintex-7 but the ChipScope trigger event does not occur - Rx_ElectricalIdle is still high.
  • Test 4 shows no transmitted OOB sequences on the cable.

Should I post parts or the complete transceiver instanziation?

only the instance has ca. 650 lines :(

Appendix:

Electrical idle means that the MGT drives both LVDS wires (TX_n/TX_p) with common mode voltage (V_cm) which is in range 0..2000 mV. If this condition is met, the common mode delta voltage is less than 100 mV, which is referred to as ElectricalIdle condition.

OOB-signaling means that the MGT transmits bursts of electrical idle and normal data symbols (D10.2 in 8b/10b notation) on the LVDS wires. SATA/SAS defines 3 OOB sequences call ComInit, ComWake, ComSAS which have different burst/idle durations. Host controllers and devices use these "Morse signals" to establish a link.

Edit 1:

After setting Common Voltage Trim (RX_CM_TRIM) and (Differential Swing Control) TXDIFFCTRL to maxima and connecting TX_ElectricalIDLE and TX_ComInit to push buttons, I was able to see some little results:

  1. TX_ElectricalIDLE is working, but the TX OOB FSM not (TX_ComInit, TX_ComWake)
  2. if TX_ComInit is high for ever, the transceiver transmitts ALIGN primitives but at a quarter of the correct clock circa 375 MHz instead of 1.5 GHz
  3. RX_Electrical IDLE is still not working

I also tried to use the alternative OOB clock, but this has no effect.

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  • \$\begingroup\$ Have you seen AR# 53364? \$\endgroup\$
    – user8352
    Aug 15, 2014 at 10:41
  • \$\begingroup\$ Yes I know this AR :) It offers only different CDR tuning parameters to support SSC. As of now, I'm using SATA Gen1 in my tests and I assigned the appropriate parameter from that list. As far as I can see, bit synchronization, comma detection and byte alignment is working in the loopback tests. But the CDR unit is far behind the OOB circuit, which is my current problem :) In parallel to this question I'm writing a simulation: testbench <=> phy-layer <=> GTXE2 <=> GTXE2 <=> phy-layer <=> testbench \$\endgroup\$
    – Paebbels
    Aug 15, 2014 at 16:02
  • \$\begingroup\$ This is very well explained question, although it is highly specialized even for users who have experience working with this kind of technology. I would suggest not entirely relying on this site for an answer. While one may come by, I would also suggest asking at a few other places to make sure you get help. \$\endgroup\$
    – Funkyguy
    Aug 19, 2014 at 20:45
  • 1
    \$\begingroup\$ @Funkyguy Hi, yes I have this question on several places posted and I'm trying to get access to Xilinx Webcases. I'm also trying to find a 20 GHz scope at university :) \$\endgroup\$
    – Paebbels
    Aug 20, 2014 at 6:59

1 Answer 1

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So I think I found some answers to the problem and want to share them.

I started to simulate the GTXE2_CHANNEL hardmacro. The simulation is behaving as "false" as the hardware. So I tried to simulate the MGT in Verilog and used an instance template from here: http://forums.xilinx.com/t5/7-Series-FPGAs/Using-v7gtx-as-sata-host-PHY-and-there-is-issue-bout-ALIGN/td-p/374203

This template simulates ElectricalIDLE conditions and OOB sequences nearly correct. So I started to diff both solutions:

  1. TXPDELECIDLEMODE, which is a port to choose the behavior of TXElectricalIDLE is not working as expected. So now I'm using the synchronous mode.

  2. PCS_RSVD_ATTR is a unconstrained bit_vector generic of 48 bit. If you have a look into the wrapper code of the secureip GTXE2_CHANNEL component, you will find a conversion from bit_vector => std_logic_vector => string. Internally all generics are treated as DOWNTO ranged. So it's important to pass a DOWNTO constant to the GTXE2 generics!

So now you could ask why is he using to-ranged constants and generics?

Xilinx ISE up to the latest version 14.7 has a major bug in handling vectors of user defined types in unconstrained generics. The default direction of vectors is TO. If you are passing vectors of enums as DOWNTO to unconstrained generics into a component, ISE is reversing the vector elements and "emits" a TO ranged vector in the components !!

This is especially "funny" if the design hierarchy, which uses this generic, is not a balanced tree...

If you are using enums of 2 elements, the problem is not existent -> maybe this enum is mapped to a boolean.

Which bugs are left?

  1. TXComFinish is still not acknowledging the send OOB sequences.
  2. I have to investigate this two bug fixes in synthesis and measure the OOB sequences with a scope - this may last some days :)

Edit 1 - more bugs:

There is an other bug in the reset behavior of the GTXE2. If GTXE2 is used with output clock dividers set to 1 (TX_ and RX_RateSelection = "000") than the GTXE2 boots up and emits only 3 clock cycles (with wrong clock period) on TX_OutClock. After that TX_OutClock is 'X'. If you reset the GTXE2 after that wrong output it boots up a second time with now error and a correct clock on TX_OutClock.

Additionally to this bug, the GXTE2 ignores all assigned resets (CPLL as well as TX/RX_RESETs) until 'X' can be seen on TX_OutClock. So you MUST wait for circa 2.5 us to issue a reset.

If you are using clock dividers with 2 or 4 (8 and 16 are not tested yet) this problem will not occur.

Edit 2 - problems solved:

Solution for Bug 1:

I have added a timeout counter whose timeout depends on the current generation (clock frequency) and the current COM sequence which is to be send. If the timeout is reached I generate my own TXComFinished signal. Don't or the timeout signal with the original TXComFinished signal from GTX, because sometimes this signal is high while COMWAKE is to be send, but this finished strobe belongs still to the previous COMRESET sequence!

Solution for an other Bug:

RXElectricalIDLE is not glitch free! To solve this problem I added an filter element on this wire, which suppresses spikes on that line.

So currently my controller is running at SATA Gen1 with 1.5 GHz on a KC705 board with a SFP2SATA adapter and I think this question is solved.

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  • \$\begingroup\$ There seams to to be an issue with the CDR circuit which is not able to recover the clock from modern devices if these use Spread-Spectrum-Clocking (SSC). The supplied RX_CDR_CFG values from Xilinx for SSC capable devices at 1.5, 3.0 and 6.0 GHz is not working. The error pattern show 3 correct data words and then one corrupted data word with bit shifts and/or flips. This pattern is periodic at 140 kHz. \$\endgroup\$
    – Paebbels
    Oct 31, 2014 at 13:40
  • \$\begingroup\$ I found a solution for the CDR configuration problem. The trick is the right control of RX_CDR_HOLD, which is neither documented nor connected the the wizards example designs! \$\endgroup\$
    – Paebbels
    Nov 19, 2014 at 20:10

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