I have some Verilog code that simulates correctly. I decided to synthesize it, and I see these warnings that make me uneasy:
Signal <> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
About 20 of the same type. I don't WANT those signals to be added to the sensitivity list, I really don't. All I want is it to do things on clock edges, not everytime a signal changes.
Giving it the benefit of the doubt, I changed my process from
always @(posedge clk or negedge reset)
And of course none of my stuff worked anymore (in simulation). Probably because the non-blocking statements are now doing stuff every time something changes, rather than waiting for clock edges.
Is there a way to prevent Verilog from doing this? I take it that it thinks my code is combinational, rather than sequential.... But why? Is there a way to tell it that this is sequential and just to use the clk?
Thanks in advance!
Edit, Here is some code, I'm cutting out some of the functionality:
always @(*) begin // Some signals here that I apparently can't put in the other one // Something about double edges end always @(posedge clk or negedge reset) begin case (!reset) 0: begin // Assign 0 to things end 1: begin p_spi_done <= spi_done; // Wants these to be in sensitivity list case ((spi_done == 1) && (p_spi_done!=spi_done)) 0: begin case (helper_reg) 5'b00000: begin // Do something else end 5'b00001: begin ... end 5'b00010: begin .... end 5'b00100: begin i_wData <= i_rDataA[SPI_WIDTH-1:0]; i_temp_reg <= i_rDataA[BANK_DATA_WIDTH-1:SPI_WIDTH]; helper_reg <= 0; end 5'b01000: begin ... end 5'b10000: begin ... end default: begin // Don't know what happened helper_reg <= 0; end endcase end 1: begin case (cpu_state) 0: begin // SYNC HAS ARRIVED if (spi_rx_data == SYNC_VALUE) begin cpu_state <= 1; end end 1: begin OPCODE <= spi_rx_data; // Instruction set begins here case (spi_rx_data) 0: begin ... end 1: begin ... end 2: begin ... end 3: begin // Set maximum count value for watch unit if (SPI_WIDTH > MAX_COUNT_LENGTH) begin n_rx <= 1; end else begin n_rx <= (MAX_COUNT_LENGTH + SPI_WIDTH/2) /SPI_WIDTH; // Compiler truncates end cpu_state <= 2; helper_reg <= 1; end 4: begin end 5: begin cpu_state <= 2; end default: begin end endcase end 2: begin // DATA case (OPCODE) 0: begin end 1: begin end 2: begin .... and it goes on in this fashion