I am interfacing LPC1768 SPI bus and SST25VF016B SPI Serial Flash. Flash is 50Mhz, and these are the values I copied from SPI Flash Datasheet. page 24.

FCLK (Serial Clock Frequency) 50 MHz

TSCKH (Serial Clock High Time) 9 ns

TSCKL (Serial Clock Low Time) 9 ns

TSCKR (Serial Clock Rise Time (Slew Rate)) 0.1 V/ns

TSCKF (Serial Clock Fall Time (Slew Rate)) 0.1 V/ns

There is also figure 26 on page 28 in the same data sheet, shows AC Test input rise/fall times are less than 5ns.

Why Clock Slew rate is so low(0.1 V/ns)? Doesn't it make clock rise and fall times very long?


1 Answer 1


The datasheet specifies that as a minimum, so higher slew rates are certainly possible (and likely). But if you slew slower than that then the device may misbehave.

  • \$\begingroup\$ Thanks for pointing that out. I think I should stop reading documentation for today :) \$\endgroup\$ Aug 16, 2014 at 23:36
  • \$\begingroup\$ I thought the slew rate was a metric used to characterize the maximum rate at which the output can change over time. According to the wiki, the slew rate is defined this way. What does a minimum slew rate even mean? The context I am familiar with slew rate is with OpAmps and with its use being to characterize the frequency response of the amplifier (to some extent). \$\endgroup\$
    – sherrellbc
    Aug 17, 2014 at 0:46
  • \$\begingroup\$ @sherrellbc: Due to the underlying analog nature of digital electronics, inputs have a minimum slew rate that must be met in order to properly recognize a transition from a low to a high or vice versa; not meeting this minimum slew rate results in misbehavior of the circuit. Some digital logic has compensation for lower slew rates, and some does not. \$\endgroup\$ Aug 17, 2014 at 2:25

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