I am trying to find a controller chip for either SRAM or S/DRAM which can properly manage access of the memory from one or more devices (i.e. microprocessors). I have been up and down Google and all I have been able to find are academic discussions and silicon level IP. What I would like is an on the market IC which can accomplish this. Speed is not particularly important, I am mostly interested for curiosity/experimentation purposes, and less for practical aspects.

  • \$\begingroup\$ Just for clarification because I'm not sure if I understand you properly. You want to have an IC that manages the RAM in a way that it can be accessed from multiple, seperate, microprocessors? \$\endgroup\$
    – Funkyguy
    Aug 17, 2014 at 3:31
  • \$\begingroup\$ @Funkyguy correct. Again, more out of curiosity than anything. \$\endgroup\$
    – Jared
    Aug 17, 2014 at 3:33
  • \$\begingroup\$ Multi-port RAM's are reasonably available. For example: idt.com/products/memory-logic/multiport-and-dual-port-memory \$\endgroup\$
    – markt
    Aug 17, 2014 at 7:18
  • 1
    \$\begingroup\$ How about I2C or SPI SRAM? Your processor or device just has to wait until the I2C/SPI bus is released before using the SRAM device, which is pretty much in the protocol. \$\endgroup\$
    – jippie
    Aug 17, 2014 at 8:53
  • \$\begingroup\$ @markt I was looking more for a separate controller but that will accomplish the goal just as well, thank you \$\endgroup\$
    – Jared
    Aug 17, 2014 at 16:18

1 Answer 1


I think what you have in mind might be a "DMA controller". DMA = "Direct Memory Access". The microprocessors will need to be DMA-compatible.

An alternative would be to use bidirectional buffers for this particular memory bank, one set per microprocessor, and some sort of "shared memory bank active" semaphore or handshake between microprocessors such that no two are trying to access the same memory at the same time (a condition that could have all sorts of bizarre side effects); shared memory access isn't super-simple to implement, and timing for controlling that semaphore would be critical.

The low-tech way of accomplishing it would be to equip each microprocessor with a slot for SD cards (of whichever footprint). Then you could "sneakernet" the shared memory.

  • \$\begingroup\$ Your alternative suggestion is how I had imagined it might be implemented. I guess I was hoping that there was some sort of device out there that implemented all this, perhaps with handshaking signals along the lines of RTS/CTS from RS-232. \$\endgroup\$
    – Jared
    Aug 17, 2014 at 3:37

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