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I've just created the footprint for a QFN-56 8mmX8mm to be used with the TLC5958.

It seems like there is some sort of isolation built in to the center pad and I cannot figure it out. In the image below, you can see that I have six vias that are to be all connected to the GND layer on the bottom. The vias are placed here just to show the issue and won't be in those spots in the finished board.

As you can see the vias show a signal connection, but for some reason the outer polygon pour doesn't connect with the GND below the IC.

enter image description here

Here are the properties of the thermal pad, from what I see, there isn't anything that would cause it to just isolate itself from everything else.

enter image description here

What property or anything could be causing this?

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  • \$\begingroup\$ Is there anything on the bRestrict layer? \$\endgroup\$ – Spehro Pefhany Aug 19 '14 at 2:05
  • \$\begingroup\$ @SpehroPefhany Nope, nothing on the bRestrict layer \$\endgroup\$ – Funkyguy Aug 19 '14 at 2:09
  • \$\begingroup\$ Are you absolutely certain that the name of the ground layer, and the name of that pad are compatible, and have not accidentally created two different grounds \$\endgroup\$ – gbulmer Aug 19 '14 at 2:10
  • \$\begingroup\$ This isn't what you asked, but the corners of the pads for the ends of adjacent rows look really really close. That tiny clearance is probably not within your board house's design rules. \$\endgroup\$ – Olin Lathrop Aug 19 '14 at 2:13
  • \$\begingroup\$ @gbulmer yep! I'm absolutely sure. I just deleted all the vias and related signals and then re-made them. The problem still stands \$\endgroup\$ – Funkyguy Aug 19 '14 at 2:17
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If you use the same default color scheme as i do, you have messed up line classes. Probably swapped tPlace and Dimension because the white rectangle is too white to be only tPlace.

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  • \$\begingroup\$ Am I to use Dimension rather than tPlace on custom parts or the other way around? Its weird that this is coming up now. I've made quite a hefty library of parts and I've never had this problem \$\endgroup\$ – Funkyguy Aug 19 '14 at 2:41
  • \$\begingroup\$ tPlace is component outline, Dimension is board outline. Poured copper keeps a gap from Dimension, that is specified in Tools/DRC/Distance or Spacing in polygon properties, whichever is greater. \$\endgroup\$ – venny Aug 19 '14 at 2:52
  • \$\begingroup\$ I was wrong, Spacing in polygon properties is for something different. Nevertheless, distance from the grey line to blue polygon is pretty close to 40 mil, which is the default value for copper/dimension distance. \$\endgroup\$ – venny Aug 19 '14 at 3:09
  • \$\begingroup\$ Turns out it was the tPlace and Dimension being swapped. I'm surprised I haven't encountered this before considering how many boards I design \$\endgroup\$ – Funkyguy Aug 19 '14 at 5:58
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My guess is that you don't have things connected right in the schematic. The ground pad should have its own pin in the symbol, and that pin should be connected to ground in the schematic. Otherwise, you are saying they aren't supposed to be connected.

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