I've just created the footprint for a QFN-56 8mmX8mm to be used with the TLC5958.
It seems like there is some sort of isolation built in to the center pad and I cannot figure it out. In the image below, you can see that I have six vias that are to be all connected to the GND layer on the bottom. The vias are placed here just to show the issue and won't be in those spots in the finished board.
As you can see the vias show a signal connection, but for some reason the outer polygon pour doesn't connect with the GND below the IC.
Here are the properties of the thermal pad, from what I see, there isn't anything that would cause it to just isolate itself from everything else.
What property or anything could be causing this?