How can I bring out the internal signals of my VHDL source code to my
testbench so that I can view them as waveforms?
A test bench implies simulation - an entity without any ports is generally not synthesis eligible.
While I've never used Active-HDL I understand it has a design browser that should allow you to pick signals down in your hierarchy to display in your waveform See Aldec's Compilation and Simulation video (5:02, min:sec).
And about now I get the impression the video may cause confusion, perhaps in this particular case.
At 2:22 from the end the video shows a do file (macro) which controls the simulation:
Where we see every signal in the top level of the design has been added to the waveform display with the wave command. It should also be possible to specify a signal in anywhere in the design hierarchy.
The basic idea is a lot of simulators allow you to schedule signals (and some allow variables) to be collected for waveform display.
This short video simply doesn't show signals for subsidiary hierarchy levels. (There's a lot stuffed in a short video presentation).
I would like to know if there is any tool independent method of achieving my objective.
As noted above your objective seems to be to view internal signals as waveforms.
Now for the bad news - there is no standardization for simulator features or interfaces, scheduling signals for waveform dump, etc.. These are all implementation defined.
It's pretty much guaranteed you can dump signals anywhere in a design hierarchy to a waveform viewer or waveform dump file with any implementation that simulates, the method for doing so is implementation defined.
The good news is they tend to copy concepts from each other such as do files, which you could generate programmatically for portability, using a common database describing functional verification on multiple implementation platforms, overcoming differences in syntax and semantics. There'd likely also be differences in command line interface syntax for invoking the tools programmatically.
The idea of portability not embracing multiple GUI's gracefully.