# Schmitt Trigger Inverter

I have this project where I'm meant to design a changing frequency circuit using schmitt triggers. It cycles between 2 frequencies. In the below circuit, pretending the not gates are schmitt inverters and ignoring the resistor and capacitor values, and letting not1 be of much much lower frequency than not2, should and output connected to not2 cycle between 2 frequencies.

IE, while not1 is low, not2 undergoes normal frequency oscillation based on it's charging capacitor C2 through R2, but while not1 is high, not2 charges at a faster rate via the added voltage through diode and R3.

Obviously buffering and whatnot would still need to be done on the output, but is the general design workable with tuning the resistor and capacitor values or not? If not, what improvements can be made? Thanks for any help.

simulate this circuit – Schematic created using CircuitLab

• IF you are allowed to use MOSFETs or bipolar transistors as well the whole game changes. If so you should say so. | IF you can accept an assymetric output then my original answer tells you how with one more diode than in your basic cct - if acceptable you should say so. Aug 20 '14 at 4:50

Design will generate dual frequency signal, but due to asymmetric nature it will change duty cycle more and it would be hard to obtain high hi/lo frequency ratio (precise parts needed).

There are other ways.

1. Use additional capacitor switched by mosfet. It may me parallel or serial to main (parallel shown).

simulate this circuit – Schematic created using CircuitLab 2. Use alternating oscillator topology.

simulate this circuit

Here on schematic second 'slave' oscillator work in two modes: when 'master' is high it is two invertor oscillator (NAND is working as second invertor); when 'master' is low NAND gate is blocked and is is acting as single schmitt oscillator.

Second schematic was discovered while playing with CD4093 quad NAND schmitt. Drawback of it that its frequency ratio hardcoded by schmitt thresholds.

• I'm going to try that first design. However, wouldn't not1 need a resistor between it's output and the mosfet to not only control current but to ensure there wasn't a direct connection to ground, thereby not charging C1? Sorry, it's probably a stupid question, I'm just really new to this sort of circuit design. Aug 19 '14 at 22:02
• Body diode in 1st cct may cause you grief. Aug 20 '14 at 4:51
• CCt 1, use two MOSFETS back-to-back / Join sources, join gates. Drive gates with NOT1, connect one drain to C3 and other to ground. Aug 20 '14 at 8:50
• Body diode will C3 to charge and reverse-bias diode. Aug 20 '14 at 10:22
• Thallazar, unlike BJTs, MOSFET gate does not consume current in static. It is more like small capacitor (from picofarads for HF to nanofarads for power mosfets). Gate resistor form RC-circuit and thus cause MOSFET to switch slower. Aug 20 '14 at 10:31

No.
As shown your circuit will tend to not do what you want.
BUT an extension of this method will.

What happens in your circuit is that when NOT1_Out is high D1 will cause the capacitor to charge faster when NOT2_output is high, and discharge slower when NOT2_output is low.
If R3 is somewhat larger than R2 this will have the effect of changing the mark space ratio but not the frequency. There will be some frequency shift but it will be a second order effect and not easily designed for. (Exponential charge and discharge rates vary with driving voltage so frequency is affected).

There are two (at least) methods that you can use:

(1) If an assymmetrical output waveform is acceptable, then placing a diode across R2 so that it conducts when NOT2_Output is low (Cathode to NOT2_output) will cause the NOT2_OutPUT_low state to be controlled mainly by the diode, so that NOT1 input will mainly affect the C1 charge time and so will alter the frequency. The output will be mostly high with a small proportion of the cycle low.

(2) If a symmetrical output is required then the effect of NOT1 being high should be to inject high voltage level when NOT2_output is high and low level when NOT2_output is low AND when NOT1_output is low it should have no effect. This causes NOT2 oscillator to run faster when NOT1_output is high. This can be achieved by resistor-diode-inverter logic alone (and a little head scratching).

Here's a 2am quick & not very checked implementation.
Circuit in dotted box shows an "easier" method.

When Oscillator 1 output is low diodes D 2 & D1 clamp IC4 & IC5 in modes such that diodes D4, D3 block and do not pas Osc2 signal back to input.
When Osc1 output is high, diodes D2 and D1 block and Osc2 signal is fed back via Rs to oppose feedback via Ro2 and this slows the oscillator frequency.

Adding an inverter between IC6_out and Rg1, Rg2 and changing diode D4, D3 polarities makes oscillator speed up when enabled. IC3 is a buffer and not strictly necessary. Gate IC3 can be removed and connections to D2, D1 moved left one step to provide the required inverter.

Thanks for the reply. I appreciate all the effort, unfortunately the frequency switching circuit needs to be as simple as possible, using as little components as possible. <5 schmitts, ideally 2-3, only as many other components as needed

A few minutes work gets a version of the above circuit down to
3 Schmitt inverters (no NAND gate so 1/2 pkg),
2 Capacitors (one for each oscillator),
4 Resistors (two for oscillators, 2 for blocking gates),
4 diodes.
Smaller is probably "hard" [tm].

To use only two inverters you have oscillators only so none or other use, so 3 seems a likely minimum.

Circuit at this stage is left as "an exercise for the student" as that is what this is about. I can add a circuit in due course.
Clues: Fast oscillator has standard feedback and also extra feedback resistor(s) that are diode connected, providing the ability to be gated off with appropriate signals. The slow oscillator supplies the appropriate signals. Diodes are used for isolation as required.

"When I was in school" [40 years ago :-) ] the figure of merit for basic gate use was "packages". So 1 package = any one of: 6 inverters, 4 x 2 input gates, 3 x 3 input gates, 2 x 4 input gates or 1 x more complex gate.