Pull up resistor

Question

I'm software, not hardware, and would ask our electronics guy, but he's away on a site visit. Someone on StackOverflow suggested I repost this here.

I get the basic idea of a pull up resistor as explained on the first few links Google throws up, but as they're used in the circuit diagram I'm looking at I'm not 100% sure. The examples I've seen all show them used along side a switch that closes to ground, so they hold the voltage up until the switch is closed. Fair enough. But here I have not a switch but the output from a flip-flop latch.

Now, when the output from the latch is low/zero, is that the same as ground? I hadn't thought so, but I don't see how else the input at the other end would otherwise ever be taken low...

                       VCC
                        |
                        |
                 PULL UP RESISTOR
                        |
                        |
                       \|/
LATCH OUTPUT ---->---------> ON/OFF INPUT FOR OTHER COMPONENT, ACTIVE HIGH

Apologies for the ASCII circuit diagram...

So assuming VCC is always on, how is the component ever switched off? The only way I can think is that the latch output being low is equal to it being a ground, but I'm not sure that's the case.

The latch component is 74AHC574 (it comes straight up on Google).

This started out as a software investigation, but we're not sure the component on the right is being power cycled as the code suggests.

Answer 1

A schematic would be helpful as there is no way to know what "the component on the right" is; however here is what I can tell you:

From the datasheet for the 74AHC574, you can see that the 74AHC574 is "OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS". The tri-state (3-state) outputs are probably the reason for the pull-up resistor. The pull-up resistor holds the output high when the flip-flop is tri-stated (/OE high). When the /OE signal is low, the output is driven either high or low depending on the output of the flip-flop. In the case where the output of the flip-flow is low, it acts just like your switch that "closes to gnd".

It should be noted that since a tri-state flip-flop is used, there could be another device that is supposed to drive the output when /OE is high. Once again, a schematic would help.

Answer 2

Take a look at the data sheet: -

When the output is driving low (trying to drive to 0V), with an 8 mA load, the specification tells you that it is guaranteed to drive as low as 0.36 volts at ambient temperature and as low as 0.55 volts at full temperature of the device.

If it's running from a 5 volt supply and the resistor is 1 kohm, the most current that resistor will be sinking into the output will be 5mA and this means V\$_{OL}\$ will be definitely below 0.36 volts at ambient.

Answer 3

Your assumtion is right: digital logic signal '0' (or 'LOW') means a connection to 'GND' (or a voltage close to 'GND').
It does NOT mean 'not connected', as many novices may think.

That's the case in most digital logic families (TTL, CMOS); there are, however, exceptions, e.g. ECL.