I have a system that boots at one frequency and then the main PLL is reloaded to continue boot at a higher frequency. When this is done, the DDR is put in to self refresh. After the main PLL locks, the DDR clock will change from 100Mhz to 133Mhz.
It seem that the DLL inside the DDR is related to the clock frequency. Should I re-run the MRS sequences to lock again before operating at the higher frequency?
Bonus: What exactly is the function of the DLL with-in the DDR? I thought everything was run off of CK/CK#. I know the host DDR controller needs some delays for latching data, but I thought DDR was designed so the RAM could be simpler.
The specific DDR2 I am using is Micron MT47H32M16 and Samsung K4T51163QG-HC.