I have a system that boots at one frequency and then the main PLL is reloaded to continue boot at a higher frequency. When this is done, the DDR is put in to self refresh. After the main PLL locks, the DDR clock will change from 100Mhz to 133Mhz.

It seem that the DLL inside the DDR is related to the clock frequency. Should I re-run the MRS sequences to lock again before operating at the higher frequency?

Bonus: What exactly is the function of the DLL with-in the DDR? I thought everything was run off of CK/CK#. I know the host DDR controller needs some delays for latching data, but I thought DDR was designed so the RAM could be simpler.

The specific DDR2 I am using is Micron MT47H32M16 and Samsung K4T51163QG-HC.

  • \$\begingroup\$ What kind of DDR? \$\endgroup\$ – mng Aug 21 '14 at 1:49

The datasheet for the RAM chips covers changing clock frequencies. For example, the Micron DDR2 datasheet says on page 40:

Operating frequency is only allowed to change during self refresh mode (see Figure 79 (page 124)), precharge power-down mode, or system reset condition (see Reset (page 125)).

There are sections in the datasheet that cover each of these situations, with timing diagrams. You should read them to understand exactly what conditions you need to meet.

Note also that the minimum frequency spec for DDR2 is 125 MHz. It may work at 100 MHz but it is out of spec and therefore not guaranteed.

As for why DLLs, according to this article it keeps the RAM simple but moves complexity into the controller. (The author's company sells memory controller IP though so they may be biased.) Since output data is aligned to CK, a DLL is needed to manage the CK to DQ output delay.

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  • \$\begingroup\$ Thanks. I just found that the Micron part was being used as a substitute yesterday and only got to page 71. It is possible that the Samsung part has a completely different procedure for frequency change and nothing is really drop-in? \$\endgroup\$ – artless noise Aug 21 '14 at 19:40
  • \$\begingroup\$ From the same section and DLL must be reset via MR after precharge power-down exit; but there is more I should be aware of. So I guess for the Micron part the answer is yes. The Samsung documents I have tell me nothing. It seems that self-refresh modes automatically perform the DLL calibration upon exit. I will probably try to start at 133MHz and not change frequency. \$\endgroup\$ – artless noise Aug 21 '14 at 20:21
  • \$\begingroup\$ In theory the parts should match the JEDEC spec (JESD79-2), and from what I can tell Micron datasheets generally match the spec closely if not word for word. So one hopes that the Samsung parts do as well. \$\endgroup\$ – mng Aug 22 '14 at 0:22

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