4
\$\begingroup\$

I'm designing a board that consists of a dspic33F, responsible for running a noise reduction algorithm and compressing audio with a Speex library, and an audio codec connected to an electret microphone and amp + speaker.

The problem I'm having is while the dspic is running the compression algorithm noise is introduced to the microphone input. My best guess as to why this happens is that the current draw resulting from the computation heavy algorithm is causing sags on the power line and I've sort of confirmed this by reducing the time in between each encode and hearing the period of the noise change as well.

So far, I've tried eliminating the noise by splitting the digital components (the dspic) and the analog components (codec, amp, mic) onto different ground planes connected only where the main ground comes in. I also have each section on its own voltage regulator, again only connected where power enters the board. I have 0.1uF decoupling caps across the VDD/VSS pins of the codec and processor, 1uF decoupling caps across the voltage regulators, and a 100uF cap across the main power line. I added these in gradually, but none seem to have made a difference.

I'm fairly certain this is all due to the processor using too much power during this one algorithm ,but I'm totally at a loss on how to fix this. Any help would be greatly appreciated

Here's the schematic, I didn't realize stackexchange would shrink it when embedded, so full size url here. https://i.sstatic.net/2Nxuy.png

And the layout, in case that's useful layout

\$\endgroup\$
15
  • 1
    \$\begingroup\$ Maybe show the analogue part of the circuitry to see if there are any particularly susceptible points but it sounds like the input to any amplifier is the likely cause of where pick-up noise is entering. \$\endgroup\$
    – Andy aka
    Commented Aug 22, 2014 at 18:29
  • \$\begingroup\$ I see you've added a layout and circuit - still not able to see the all important analogue parts of the circuit and is it a double sided board with no apparent analogue earth plane at all? \$\endgroup\$
    – Andy aka
    Commented Aug 22, 2014 at 19:15
  • \$\begingroup\$ Sorry, I've updated it. The bottom layer is split in two for digital and analog ground planes, joined in the upper right corner \$\endgroup\$
    – Dav
    Commented Aug 22, 2014 at 19:23
  • 1
    \$\begingroup\$ If you think that the power consumption from heavy processing is causing your noise, I'd think that disabling that processing and seeing if that noise remained would be an OK debugging step \$\endgroup\$ Commented Aug 22, 2014 at 19:28
  • \$\begingroup\$ I've done that. I get much less noise when I'm only decoding data coming into my board to be played. However if I'm encoding sound, either alone or with decoding at the same time, my problem arises. \$\endgroup\$
    – Dav
    Commented Aug 22, 2014 at 19:34

3 Answers 3

2
\$\begingroup\$

C12 should not connect arbitrarily to a local ground but should connect directly to the microphone ground on J2: -

enter image description here

That's my 1st observation - when you have MICN and MICP pins they need to route side by side to minimize pick-up also. The big problem with where C12 is grounded is that between its ground point (junction of C7 and C5) there could exist several hundred micro-volts of high frequency ground noise due to currents in the ground plane. This is why that chip provides a mic-negative pin - it uses a differential amplifier to amplify the mic signal directly.

There may be other issues like C5 also not connecting directly to the mic ground on J2 also. C7 and C6 also must ground right at the microphone negative point too. Also R4 causes the MICP lead to be very long and clearly, the longer the microphone tracks are, the more they'll pick-up.

\$\endgroup\$
2
  • \$\begingroup\$ So, if I'm understanding you right I completely screwed up my grounding? I was afraid of that. \$\endgroup\$
    – Dav
    Commented Aug 22, 2014 at 20:45
  • \$\begingroup\$ Maybe - try isolating the via that grounds C6, C7, C5 but leave C15 still grounded to the via and see if there is an improvement. Hopefully there is and don't forget to tie C12 directly to the mic pin also. \$\endgroup\$
    – Andy aka
    Commented Aug 22, 2014 at 20:54
3
\$\begingroup\$

Your main issue arises here:

enter image description here

You have traces that bridge your ground plane split with out a clear path for the image current flow. And some of these signals are very fast with sharp edges. You need to think in terms of return current flow, how does the current flow to return to the ground/power pins on the package? with that slot there you are forcing them to flow up and around a nice slot antennae and are also forcing them to interact magnetically.

To test this, short out the two planes by scrapping off solder mask, and soldering some desoldering braid across the gap, shorting out the analog and power planes in that area and providing location for the current flow. This will also reduce your EMI/RFI.

I haven't bother ed to look at other areas yet so there could be other possible problems. But work on this one area and you'll see improvements.

\$\endgroup\$
1
  • \$\begingroup\$ I've done this, but it doesn't seem to have helped, unfortunately \$\endgroup\$
    – Dav
    Commented Aug 23, 2014 at 15:03
1
\$\begingroup\$

Your schematic is too small to read, but this strongly smells just like bad grounding.

Your layout looks like the bottom layer is meant to be a ground plane to the extent possible. That's fine, but I see no attempt at local grounds for the separate subsystems, particularly the noise-generating dsPIC. That means all the high frequency power currents of the dsPIC are running accross your main ground plane. Connect all the ground points immediately around the dsPIC together, then connect this net to the main ground plane in one single place. Then put a larger secondary bypass cap accross the overall power and ground feedpoints of the dsPIC subsytem.

As for anything that is analog and sensitive, filter the supply a little and bypass it to the main ground plane local to that subsystem. A small 0805 chip inductor in series followed by a 20 µF ceraming cap to ground should eliminate a lot of noise from the supply.

\$\endgroup\$
1
  • \$\begingroup\$ I didn't realize stackexchange would resize embedded images so I included the link to the full size image. I thought that I had tied all the ground points together onto a local net under the dspic which is tied to its ground plane through that via (close to the label U1). Did I do this incorrectly? \$\endgroup\$
    – Dav
    Commented Aug 23, 2014 at 12:55

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.