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Why for low power consumption width of NMOS taken same as length of feature and Width of PMOS taken as 2.5 times width of NMOS ? e.g for feature size 180n width of NMOS 180n and width of PMOS 450n. Is there is any mathematical equations that support this concept?

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  • \$\begingroup\$ Could you add a reference to your source if information to your question? \$\endgroup\$ – gbulmer Aug 23 '14 at 16:13
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The width differences arise from the difference in mobility of the electrons and holes with holes being a factor of ~2.2 slower than electrons.

\$ \frac{W}{L} \mu_e = \frac{W}{L} \mu_h \$

Having balanced \$ g_m\$ on teh PMOS and NMOS will give symmetrical rising and falling edges times. Which is not a necessary condition for low power as you state. Low power design arises through other mechanisms.

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  • \$\begingroup\$ +1 Electronic faster than holes. CPU was one giant step faster when changed from PMOS (Intel 4040) to NMOS (8080) and the rest is history. A big jump from 0.6 to 2MHz. \$\endgroup\$ – EEd Aug 23 '14 at 18:02
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Much of the time Complementary MOS (CMOS), i.e. circuits built using P-Channel and N-Channel MOSFETs, is not conducting.

The power consumption is mainly during switching from one state to the other. N-Channel MOSFETs will either use less power to switch, or will switch faster than P-Channel MOSFETs for similar geometry. (PMOS is 'slower' than NMOS, because 'holes' are slower than electrons)

I might expect the area of PMOS to be bigger because NMOS conducts much better. Increasing the area of a MOSFET will reduce its on-resistance, and I assume, indirectly, improve the switching time of subsequent CMOS gates.

So I would expect MOSFETs to be manufactured in such a way that the switching time of the two complementary MOSFETs more closely matches each other. That might be achieved by making the n-Channel MOSFET smaller, or the P-CHannel MOSFET bigger.

However, I would not expect the difference to be quite so big. That is a factor of over 6.

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  • \$\begingroup\$ There is a lot of incorrect assumptions here. In static logic designs either the NMOS or the PMOS is conducting, it's only when both are on that you get shoot through current or capacitor charging current on change of state. Even in the steady state though one of the transistors is at least conducting i.e. tying the output to one rail or the other. In your second paragraph "using less power" and " switch faster " are inversely related, you need to pick one or the other, not both. Increasing the width increases transconductance and directly improves switching as \$ \dfrac{g_m}{C}|$. \$\endgroup\$ – placeholder Aug 23 '14 at 22:04
  • \$\begingroup\$ @placeholder - "There is a lot of incorrect assumptions here". Agreed. Clearly the or in "use less power to switch, or will switch faster" wasn't clear enough. Is "either ... or" adequate? I am focusing on charging the gates of subsequent MOSFETs, as that is the vast majority of MOSFETs in an MCU. You seem to be suggesting that a manufacturer would not attempt to match PMOS and NMOS, by using different sizes of device, yes? \$\endgroup\$ – gbulmer Aug 23 '14 at 23:49

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