After looking at various designs for a "software" controllable power off circuit for a Raspberry Pi computer I decided none of them fit my need so I designed my own. Before I commit it to a PCB for manufacture, I would like to ask whether anyone sees any obvious problems with the circuit and the description below:

Background: I am designing an embedded controller which includes a Raspberry Pi compute module, an ARM Cortex M3 MCU, and it needs to drive a number of high current loads (motors). The board is to be powered by a 24V high current supply.

Requirements are that the board will power on when the momentary power button is held down for a second or so. The board shall initiate a shutdown procedure when the power button is pressed and held low for a second or so again.

A shutdown procedure is required in order for the compute module to properly exit application code and save state to memory.

My solution is in the diagram below:

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As the on/off momentary switch is held low, the system receives 24V through the Schottky diode D1. Regulators start up, and MCU and compute module start booting (all within a few milliseconds). The first thing the compute module does upon power up is drive GPIO 8 HIGH. This signal is buffered by U1 and it activates FET Q1 which latches the power on. The momentary switch does not need to be pressed any longer. Capacitor C1 maintains charge on Q1 in case GPIO 8 accidentally flickers from the HIGH state during the startup process.

D2 is a flyback diode for the solenoid.

Another press on the ON/OFF button results in ~3V appearing on the A terminal of buffer U2, due to resistor divider R4/R5. This signal is buffered and passed to compute module GPIO pin which is setup to interrupt on rising edge hence generating a shutdown software command.

The last thing the software does upon shutdown is drive GPIO 8 LOW, hence turning off Q1 and unlatching the relay, cutting the power to the PCB.

The question is whether my logic is sane, and whether anyone has spotted any problematic areas on the schematic?


1 Answer 1


U1 needs a pull-up or pull-down resistor on the input for when GPIO8 is low. I'd make R4 and R5 lower in value in case the switch needs a minimum wetting current to keep its contacts fresh and deoxidized (although if the regulators are connected this should be ok). I don't know what R3 is doing.

I'd put a capacitor to gnd on the switched 24 V side to ensure that power stays up even if the button press is a little short in duration. I'm struggling to see what D1 achieves.

Bottom line for me is simulate it first before committing to a PCB.

  • \$\begingroup\$ Hi Andy, thanks for the answer. R3 is a pulldown on the gate of the MOSFET. When power is off, output of U1 and gate of the FET are both high Z. Any induced or remaining voltage would trigger the FET. It is also a discharge path for capacitor C1. D1 is essential as without it there would always be 24V on the A side of the ON/OFF switch making it impossible to detect a second button press. \$\endgroup\$
    – IgorEE
    Aug 24, 2014 at 17:11

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