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Context: tuning the control loop of a buck SMPS. I specicifally have a TI TPS40200-based circuit in mind, but I think this applies to SMPS design in general.

Quoting from Type 2 compensation network:

Mr. Maniktala suggests that the loop gain transfer function of the switcher intersect
the 0 dB point at approximately 1/6th the switching frequency, with a slope of -1.

I have heard this before from another engineer, but did not get a chance to ask why. What is the reason the crossover frequency of the control network should be a fraction of the switching frequency? Why specifically around 1/5th or 1/6th?

Are there any other desirable traits when designing a compensation network for an SMPS controller other than the most basic criterion of >45 degree phase margin for system stability?

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A switch mode power supply is essentially a sampled-data system, therefore the theoretical maximum bandwidth is one half the switching frequency. Practically the phase and transport lag there make it impossible to close the loop there, so 1/5 to 1/10th the switching frequency is a good rule of thumb.

There are many other considerations in compensating an SMPS- Gain margin, conditional stability, current vs. voltage mode, slope compensation, transient response, etc.

Check out www.ridleyengineering.com, there are lots of good free tutorials and papers there.

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    \$\begingroup\$ Ah. So I was overlooking the fact that a sampled-data system need not be a digital control system. You can only update a PWM duty cycle once per period, and that makes this a sampled-data system because you output is sampled, even if the controller itself is almost completely analog circuitry. This is a case where the terms 'discrete-time' and 'digital' are far from interchangeable. \$\endgroup\$ – Dmitri Aug 26 '14 at 19:27
  • \$\begingroup\$ Exactly! You can use a zero-order hold transfer function in the z domain as part of the control loop model of a SMPS to model the sampling effects. \$\endgroup\$ – John D Aug 27 '14 at 3:05

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