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I'm using a FXLS8471Q accelerometer for a project using the SPI interface. The chip uses the same pins for SPI and I2C. To detect which interface the user desires, the chip samples the SA0 pin on power up according to Table 11: enter image description here

I have two questions.

  1. To make the SA0 pin appear floating, I connected it directly to the input of a CMOS buffer. The buffer I chose happens to be of the 74LVC series. Since the input to a CMOS device is basically connected directly to the gates of MOSFETs, am I correct in assuming that a CMOS input will "look like" a floating pin to this chip?

  2. What is the internal circuit that the manufacturer likely used to detect a floating pin? One thought that comes to mind is a simple 50/50 resistor divider between power and ground. Sampling the middle of the divider with an ADC or two comparators could tell the difference if the pin is tied high, low, or floating. Is it much more complicated than that?

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ To make a pin appear floating, you can just leave it unconnected. Detection is probably not done by voltage divider, because in general, digital inputs do not like voltages between high and low logic level. More likely it is done by switching between internal pull-up and pull-down resistor. \$\endgroup\$ – venny Aug 29 '14 at 22:50
  • \$\begingroup\$ Unfortunately the SA0 pin is also the SPI MISO pin, so it must be connected in my circuit to use SPI. \$\endgroup\$ – Dan Laks Aug 29 '14 at 22:51
  • \$\begingroup\$ Oh, now i see it. Then it is correct. Or wire it directly to MISO of the host MCU that has its pull resistors disabled. \$\endgroup\$ – venny Aug 29 '14 at 22:57
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I suspect they use a sequential method where they weakly drive the pin high and low and sample the states. There are four possibilities in the truth able, one of which should never happen.

Since they do not seem, to be too concerned about floating outputs connected to SA0, a reasonable CMOS input should be okay- but I'd be concerned about long conductors with a lot of capacitance.

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    \$\begingroup\$ Do you have any citation? \$\endgroup\$ – venny Aug 29 '14 at 23:00
  • \$\begingroup\$ @venny citation re tri-stated outputs connected? Refer to the relevant section of the data sheet. \$\endgroup\$ – Spehro Pefhany Aug 30 '14 at 4:07

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