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I want a counter that the Most significant bit toggles every 2 seconds, and gets values 0 and 1.So for example it will have 0 for 2 seconds and after 1 for another 2 seconds etc.. I need it like that because I will connect the most significant bit to a decoder which will show results on FPGA 3starter (50MHZ/20ns) Does this will work?

 library ieee ;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

----------------------------------------------------

entity counter is

generic(27: natural :=2);
port(   clock:  in std_logic;
    rst:    in std_logic;
    count:  in std_logic;
    Q:  out std_logic_vector(27-1 downto 0)
);
end counter;

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architecture behv of counter is           

    signal Pre_Q: std_logic_vector(27-1 downto 0);

begin

    -- behavior describe the counter

    process(clock, count, clear)
    begin
    if clear = '1' then
        Pre_Q <= Pre_Q - Pre_Q;
    elsif (clock='1' and clock'event) then
        if count = '1' then
        Pre_Q <= Pre_Q + 1;
        end if;
    end if;
    end process;    

    -- concurrent assignment statement
    Q <= Pre_Q(27-1);

end behv;
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  • \$\begingroup\$ depends on your clock frequency. NOt the best way to code a counter \$\endgroup\$ – JonRB Aug 31 '14 at 15:35
  • \$\begingroup\$ @JonRB my inside clock on FPGA is 50Mhz/20ns \$\endgroup\$ – user Aug 31 '14 at 15:41
  • \$\begingroup\$ @JonRB no it's not duplicate.I am not the same user. \$\endgroup\$ – user Aug 31 '14 at 17:29
  • \$\begingroup\$ It isn't necessary that you are the same user, I think it is sufficient that it is the same question. The idea of the stackexchange wiki format is to have a good set of questions and answers, and avoid duplicate questions. The question @JohnRB links to seems to be the same as this question. \$\endgroup\$ – gbulmer Aug 31 '14 at 17:32
  • \$\begingroup\$ @gbulmer Here It's not 2Hz but 0.5 Hz \$\endgroup\$ – user Aug 31 '14 at 17:43
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You're very close, so I'm going to give you the answer here. Let me know if you have any further questions.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

----------------------------------------------------

entity counter is

generic (
  width: natural := 27;
  max_count: natural := 100_000_000     -- 50 MHz / 0.5 Hz
);
port (
  clock:  in std_logic;
  rst:    in std_logic;
  count:  in std_logic;
  Q:      out std_logic
);
end counter;

----------------------------------------------------

architecture behv of counter is           

  signal prescaler: std_logic_vector(width-1 downto 0);
  signal pre_Q : std_logic;

begin

    -- behavior describe the counter

  process (clock, count, clear)
  begin
    if clear = '1' then
      prescaler <= (others => '0');
      pre_Q <= '0';
    elsif (clock='1' and clock'event) then
      if count = '1' then
        if prescaler = max_count then
          -- This happens every 2 seconds; toggle the output flip-flop.
          prescaler <= (others => '0');
          pre_Q <= not pre_Q;
        else
          prescaler <= prescaler + 1;
        end if;
      end if;
    end if;
  end process;    

    -- concurrent assignment statement
    Q <= pre_Q;

end behv;
| improve this answer | |
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  • \$\begingroup\$ The count input was in your original code, so I kept it. It functions as an "enable" signal for the counting, so you would ordinarily just tie it high. Yes, Q is the output that toggles every 2 seconds. \$\endgroup\$ – Dave Tweed Aug 31 '14 at 17:44
  • 1
    \$\begingroup\$ You copied that code from the question that @JonRB cited. \$\endgroup\$ – Dave Tweed Aug 31 '14 at 18:00
  • \$\begingroup\$ Yes but I have edited it. \$\endgroup\$ – user Aug 31 '14 at 18:00
  • \$\begingroup\$ BUT the principal is the same. asking for a 2Hz strobe isn't much different from asking for a 0.5Hz strobe \$\endgroup\$ – JonRB Aug 31 '14 at 18:22
  • \$\begingroup\$ @DaveTweed are you sure that this will work ?? it will show 1 or 0 because I want to get the MSB for seven segment displays. \$\endgroup\$ – user Sep 1 '14 at 15:14

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