module stimulus; wire [3:0] max,med,min; reg [3:0] a,b,c; reg cin; sorting_three three(max,med,min,a,b,c,cin); initial begin a=4'b0010; b=4'b1001; c=4'b1010; cin=1'b0; end endmodule
The above code giving correct result after Simulation. When I try to view RTL schematic. Its is giving error like:
ERROR:Xst - "stimulus.v" line 22: Module has no port. --> Total memory usage is 123976 kilobytes Number of errors : 1 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) Process "Synthesis" failed
How to define port of stimulus( it is test bench)? I think wire and reg is sufficient to define input and output port. If it is not then what correction required to get correct RTL schematic.