# how to define port in test bench?

module stimulus;
wire [3:0] max,med,min;
reg [3:0] a,b,c;
reg cin;
sorting_three three(max,med,min,a,b,c,cin);

initial begin
a=4'b0010;
b=4'b1001;
c=4'b1010;
cin=1'b0;
end
endmodule


The above code giving correct result after Simulation. When I try to view RTL schematic. Its is giving error like:

ERROR:Xst - "stimulus.v" line 22: Module  has no port.
-->

Total memory usage is 123976 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

Process "Synthesis" failed

How to define port of stimulus( it is test bench)? I think wire and reg is sufficient to define input and output port. If it is not then what correction required to get correct RTL schematic.

• You shouldn't be synthesizing a testbench anyway. A testbench module is meant to be used in simulation only, to represent parts of the application that are outside the module(s) being tested. Think about it -- a module that has no outputs synthesizes to zero logic, no matter how complex the code inside might be. – Dave Tweed Sep 1 '14 at 14:06

module mymodule(port_a, port_b);

module stimulus();

• Not completely correct. You can have module stimulus; without the (). – dave_59 Sep 2 '14 at 15:22