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I've built quite a few circuits but I've never really designed anything from a "schematics first" approach. Mostly just tinkered with designed and code until I got it right.

Now, I want to build a horizontal timer circuit for an NTSC computer project I am working on.

Anyway, assuming I have a 74xx4040 12-bit ripple counter that is clocked at 7MHz I want to enable other circuits when the master counter (the 74xx4040) reaches certain values. The counter would count from 0 to 447 and on the 448th value reset to 0.

During those 448 counts, I have identified the following bit values as my "trigger" points. These are the 4 MSB's.

0001 00000  (32)
0010 00000  (64)
0011 00000  (96)
0100 00000  (128)
1100 00000  (384)
1110 00000  (448) -- RESET

Other than putting a crazy amount of AND/NAND/NOR/etc. gates connected to the 4 MSB's, is there a simpler way? I only have 2-input gates available (AND/NAND/NOR/XOR/etc.).

My thinking is that each area of the circuit would be clocked by the same 7MHz clock. And as the master counter reached, say 96 for example, the first 4 bits (0011) would turn on the CE pins of all of the other IC's for that section. And when the master counter reaches 128 (0100) then only that section would be enabled and the CE of the previous would be disabled.

Hope that makes sense.

Is this a practical/sane way of approaching this?

Thanks

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  • \$\begingroup\$ So you want to generate a reset signal (HIGH) when 3 bits are high, using only 2-input gates? two inputs into AND gate 1, its output and the third bit into AND gate 2. \$\endgroup\$ – gbulmer Sep 8 '14 at 21:00
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    \$\begingroup\$ Using a ripple-carry counter like the 4040 will result in glitches in the decoded outputs, so you should latch the decoded output on a following clock edge if you're using it for something like an asynchronous reset. \$\endgroup\$ – Spehro Pefhany Sep 8 '14 at 21:07
  • \$\begingroup\$ @SpehroPefhany - ah! So it needs the top 4 bits to be latched before they are used. \$\endgroup\$ – gbulmer Sep 8 '14 at 21:12
  • \$\begingroup\$ You can latch the bits, or latch the decoded outputs, whatever you like. \$\endgroup\$ – Spehro Pefhany Sep 8 '14 at 21:15
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With only simple logic gates, you're going to be "putting a crazy amount of them" on the four MSBs. Optimizing your logic can help reduce the number of gates (there are two that start with 11, so they can share some gates, for a start).

However, if you were to spend a few pence and invest in a 74xx154 4-to-16 decoder then the 16 possible combinations of MSBs would be presented to you as one of 16 outputs being pulled low. Much neater than lots of gates.

If you can't get a 154 you could use two 74xx138 chips and use the highest MSB bit to choose between them.

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