Considering a npn transistor, when it is active the electrons at the base (which came from the emitter) is swept into collector as the collector is at a higher voltage level. In case of saturation, the electrons at the base do not enter the collector as active mode as the collector cease to be at a higher voltage level. So, the collector current reduces as the bcj is forward biased more than 0.5 approx. Now, my ques is, how to the transistor show low resistance path between collector and emitter in saturation. Since, the collector emitter voltage is quite low at saturation and so is the collector emitter resistance, there is almost a short path at saturation. How is it possible, since the electrons can't even get to enter the collector?
\$\begingroup\$ A transistor at rest has two depletion regions. \$\endgroup\$– Ignacio Vazquez-AbramsSep 9, 2014 at 14:49
Remember the V(CE) vs I(C) curve and consider an NPN transistor. Thus forward biasing simply means there is positive voltage on the p-type junction relative to an n-type junction.
Thus, in our case forward biasing the BC junction means having a voltage V(BC) > 0.
Now, when collector voltage V(C) drops below the base voltage V(B) and forward biases the collector‐base junction (when V(BC) > 0):
The strong electric field which opposes the movement of the charged particles into the collector is now weakened.
There is now a numerous charged particles into the collector, hence current increases and the current gain factor, β, decreases.
This corresponds to a logical more of "0" where the transistor acts as a switch, showing a low resistance path for current conduction.
Electrons have no trouble entering the collector, since even at saturation, there still a small positive bias on the collector. If this bias disappears, then all of the emitter current will flow to the base.