I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead

Some of the information they have provide is the list of PAR Output Files and the ISE Design Suite Files in the Command Line Tools User Guide, the source files list from here.

Edit Aug 19 2011: mentioned 13.2 and PlanAhead Edit Sep 7 2011: removed EDK reference since some in answer

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    \$\begingroup\$ As far as I know they are moving to write from scratch all software tools they already have...so probably such list become obsolete in a year and half \$\endgroup\$
    – doubleE
    Commented Aug 3, 2011 at 20:47
  • \$\begingroup\$ Don't you create the input files, and therefore know their names and suffixes? You shouldn't need to know the names of the output files to ensure that the input files are in source control. I'm not familiar with your workflow, so this is a little confusing to me. \$\endgroup\$ Commented Aug 17, 2011 at 22:58
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    \$\begingroup\$ Most version control operates on a blacklist rather than whitelist principle for deciding which files are candidates for version control. For example, in Mercurial, there is the .hgignore file which contains a list of regular expressions specifying which files to exclude. Subversion uses a property named svn:ignore which only affects the directory it is set on. Thus, to keep other users from checking in all the build trash (which often causes collisions during updates and merges), you have to have a list of suffixes to exclude. \$\endgroup\$ Commented Aug 20, 2011 at 2:58
  • \$\begingroup\$ @Kevin Vermeer: Not exactly. There are other utilities such as CoreGen that generate some files. And those have both outputs (e.g. reports) and inputs (e.g. settings for the generator) \$\endgroup\$ Commented Aug 20, 2011 at 3:57
  • \$\begingroup\$ As @Arash pointed out they rewrote their software in May 2012, now called Vivado press.xilinx.com/… \$\endgroup\$ Commented May 1, 2012 at 18:33

4 Answers 4


Quick answer: No such list exists, anywhere.

Long answer: I could tell you, but then I'd be wrong. I've been using Xilinx tools for the past 15+ years and every time they come out with a new version (or even a new service pack) things change. Sometimes even just changing various XST/MAP/PAR options will cause new files to be generated. So even if I did give you a list it would likely be out of date or just wrong.

I've created my own makefiles for building my FPGA's (I'm not using ISE's GUI environment), and it's fairly well documented what the input files to the various tools are (XST, MAP, etc). Everything else is not required and thus doesn't need to be checked into the source control system. My makefiles have a "make clean" option that removes all of the extra files. So when Xilinx releases a new version I simply recompile and the "make clean". Any file that remains (and isn't obviously something I need) is considered to be junk, and I add those files to the "make clean" list of things to delete.

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    \$\begingroup\$ Yes, this is sadly often a HUGE problem with integrating fancy IDE's into structured engineering practice. \$\endgroup\$ Commented Aug 3, 2011 at 4:13
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    \$\begingroup\$ @David Kessner Good post. Any chance you could post one of your makefiles? \$\endgroup\$
    – Jim Clay
    Commented Feb 1, 2012 at 17:47
  • \$\begingroup\$ @JimClay Sorry, but I can't. Not only are my makefiles way more complicated and confusing for most peoples use, they are also done for my job and thus copyrighted and stuff. \$\endgroup\$
    – user3624
    Commented Feb 1, 2012 at 18:10

Here's the start of a community wiki for the suffixes. I agree with @David Kessner. Xilinx also has this list from the command-line tools document and published a list here and here (for earliers version of their software).

File Suffix,Input or output,description
asy,output,symbol file
bat,input,batch file. Some are generated by PlanAhead
bgn,,bitgen report file
bit,output,FPGA bitstream
blc,output,NGCBuild report file
bld,output,build report from NGDBuild
bmm,,blockram files
cdc,input,ChipScope file 
cfi,input and output,provides info to Support for Platform Flash PROM Design Revisioning
cgc,,ChipScope file
cgp,,Coregen project file
cmd_log,output,log file
css,output,HTML file
csv,output,pin list
ctj,,trigger file for ChipScope
do,input,simulation script
drc,output,design rule check
edf,output,EDIF netlist
edif,,see edf
edn,,an EDIF file suffix
f,,used for functional simulation
filter,,used in ISE to filter messages
gise,output,"contain generated data, such as process status" per http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_understanding_ise_project.htm
hdx,,used in PlanAhead for partitions
html,,report file
ipf,input,impact (programmer) project
isc,output,Configuration data in IEEE 1532 format.
js,output,JavaScript for some HTML report
ll,output, Readback information; created by bitgen
log,output,log file
lso,input,library search order input  to XST.
make,outout,from EDK tools
map,output,report file
mcs,output,prom file
mhs,,(EDK) Defines system
mrp,output,report file from map
mif,input,memory initalization
mpd,,MicroProcessor Definition (EDK)
msd,output,Mask information from bitgen; used for verification
msk,output,mask information from bitgen; related to .bit
ncd,output,Native Circuit Description; after map process; used as bitgen input
ncf,,constraints for a core
ngc,output,used by NGDbuild
ngo,output,intermediate netlist from NGDBuild
ngr,output,RTL schematic generated from XST
nky,,encryption key file, used by bitgen
nlf,output,ASCII NetGen NetGen log file that contains information on the NetGen run
nmc,,physical macros; used by NGDBuild
opt,,EDK generation options
pad,output,list of I/O pads/pins
par,output,Place and route log
pcf,,physical constraints file; used by bitgen
pdf,output,Acrobat document for core
ppr,,PlanAhead project file
prj,input,project file
prm,,PROM file generation control file
prn,output,exported ChipScope .csv file. Often lacks that suffix.
psg,output,PlanAhead strategy file
ptxw,,twx file which project navigator uses for parsing 
pxml,,associated with partitions
rba,output,read back file created by bitgen; binary
rbb,output,read back file created by bitgen; ascii
rbd,output,read back file created by bitgen; data only
rbt,output,bit file in different format
runs,,directory in PlanAhead
scr,,XST synthesis script
sdbx,,Installation files
sdc,input,timing file [thanks @trondd]
sh,input,Linux shell script. Some are generated by PlanAhead
srcs,,directory in PlanAhead
srp,output,Synthesis log file
sym,output,Core symbol file
txt,output,log file
twr,output,timing report
ucf,input,constraints file
unroutes,output,report file
urf,input,User Rules File; used by NGDBuild
v,input or output,Verilog file for code. Output of coregen
veo,output,Verilog timing simulation file
vhd,input or output,input source VHDL file; output from Coregen
vho,output,VHDL timing simulation.
wcfg,input,ISim waveform configuration file
xaw,output,generated by Coregen
xco,,use by Coregen to regenerate cores. Contains core's parameters
xise,,created by coregen
xlsx,,some report
xml,,some are output reports
xmsgs,output,log file
xreport,output,report file
xrpt,output,report file, others are inputs to PlanAhead
xsf,,symbol file for Mentor
xst,output,associated with HTML file?
unroutes,output,report file
wbd,output,Waveform Database
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    \$\begingroup\$ The sdc file is listed as output, but this is usually an input file to the timing analyzer (TimeQuest in the Altera world). The file usually is handwritten and should therefore be in version control. \$\endgroup\$
    – trondd
    Commented Aug 18, 2011 at 18:56
  • \$\begingroup\$ Thanks for providing a comprehensive list. I wanted to know if there was any revision to this list as the post is about 4.5 years old now. \$\endgroup\$ Commented Oct 6, 2021 at 5:10

I've created a project on Github called X-MimeTypes which aims to provide a basis which the community can use to once and for all create a proper knowledge base about the file types used in the EDA industry.

This approach has some advantages over just listing all known files in a list as done in the previous answer:

  • Its on Github, thus its open and its version controlled so that you can view a full history.
  • The format used matches that of the OpenDesktop mimetype database. Again, there are many advantages in using this approach.

    • It is proven.
    • It can be extended. The current extensions allows each type to be marked as generated or not. Very useful for version control and cleanup operations etc.
    • On Linux you can add this file to your system's mime database and all programs will recognize the types in the file.
    • It supports the ability to classify files using magic headers etc. An example of why this is necessary is a Xilinx binary configuration file which ends with *.bin. The standard mime type database defines a .bin file as application/octet-stream, thus it will be handled as a normal binary file and it won't be picked up as a Xilinx binary configuration file. The mimetype specification easily solves this problem using magic headers. Thus, a possible correct mimetype definition for a Xilinx .bin file is:
  <mime-type type="application/vnd.xilinx.bitgen.binary_configuration_file">
    <comment xml:lang="en">Xilinx Binary Configuration File</comment>
    <glob pattern="*.bin"/>
    <magic priority="60">
      <match type="string" value="\xff\xff\xff\xff" offset="0"/>
  • Anyone can file bugs against the repository, clone it etc.
  • Its not vendor specific.

The EDA mime types can be accessed here.

Such a project really requires the power of the crowd, thus each small contribution will make the database more useful to many FPGA designers out there.

  • \$\begingroup\$ I do not think Xilinx qualifies directly as an EDA software, but thanks for the github repo having the various lists. \$\endgroup\$ Commented Oct 6, 2021 at 5:05

Another solution to sort the input files from the output files this:

1) Build the FPGA

2) import everything into a version control system (e.g. git init; git add .; git commit -m "init";)

3) rerun the FPGA build

4) all modified files ('git status') after the second run are most likely to be output files (inc. log files, ...) and the non modified once are the input files.

This is what I do when I receive a directory or zip-file with the message "this is the project, please fix it..."

  • \$\begingroup\$ 4) mostly works. But sometimes they update files with a last compiled time in the file itself. That makes this step not as good as I would like. \$\endgroup\$ Commented Feb 25, 2013 at 20:53
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    \$\begingroup\$ @Brian Carlton Do you talk about input files that are updated with a modification time. E.g. XCO files from Coregen. Indeed, here fails my method. I prevent the tools to modify those kind of files by doing a 'chmod -w' on those files in the Makefile. \$\endgroup\$
    – vermaete
    Commented Feb 26, 2013 at 5:50

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