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I consider using a cheap Microchip 3-pin EPROM with single bidirectional data line as ID storage on various daughter boards.

Since I don't want to waste daughter board connector pins on a device that will be used only once during initialization I was thinking about powering the EPROM from the active-high Reset pin of each daughter board, while using another IO that is unused during init as the data line. After init the reset line goes low and the EEPROM shuts down. However, for this to work the EPROM need not interfere with normal operation that is it does not draw parasitic current from the IO during normal operation. Can someone suggest a solution?

Edit: the device in question is a 11AA010 with 1mA active current and 1uA standby current as per datasheet.

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    \$\begingroup\$ A datasheet or partnumber for the EEPROM would be helpful. \$\endgroup\$ – Dejvid_no1 Sep 12 '14 at 19:02
  • \$\begingroup\$ Will the IO pin that is used to read the EEPROM be multi-purposed for other functions after reset? Also, how much current does the EEPROM use when powered on? \$\endgroup\$ – Dan Laks Sep 12 '14 at 19:04
  • \$\begingroup\$ @Dejvid_no1 see my edit \$\endgroup\$ – Arne Sep 12 '14 at 19:31
  • \$\begingroup\$ @Dan yes the IO pin will be used otherwise \$\endgroup\$ – Arne Sep 12 '14 at 19:32
  • \$\begingroup\$ Will 1uA and 7pF really disturb the rest of the circuit that much? \$\endgroup\$ – Ignacio Vazquez-Abrams Sep 12 '14 at 21:08
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It is out of specification of the part to have the SCIO pin be more than 1 V higher than the VCC pin. From the "Absolute Maximum Ratings" section of the data sheet:

SCIO w.r.t. VSS ...... -0.6V to VCC+1.0V

Therefore it might damage the part if you apply 3.3 V to SCIO while VCC is at 0 V. But either way, if it breaks, you get to keep all the pieces since you violated the Absolute Maximum Ratings.

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