For a homework assignment I need to
Redesign the right-shift register circuit of Figure 12-10 using four D flip-flops with clock enable, four 2-to-1 MUXes, and a single OR gate.
The figure mentioned has three states, No change, Load, and Right shift. The loads are each from different inputs. I have been able to figure out how to do any two of these states without the OR gate, but I can't seem to figure out how to get all three to work. I suspect that I need to somehow stop the clock when I want to achieve the "No change" state.