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Can you guys provide some feedback on my layout for this TP562200 buck regulator? I'm using it to take a ~12V and drive a servo. The supplied resistor values should provide about 5.1V, which is within the range of what the servos want. This will be used on a board that's got some sensitive components (GPS, sensors, etc.), and controlled by an ATMega2560. I'm only turning the regulator on when I need to drive the servos (which is typically a few times per minute).

I've tried to follow their reference design and reference layout (pages 13 and 21 respectively). I'm including them here for convenience:

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One thing that confused me is that their reference design includes two input caps and two output caps, while their reference layout has 1 of each. I opted for the former.

My schematic:

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My layout. The plane on the top left is V_OUT, top right is V_BATT, and top center is ground. The bottom layer is ground as well. The trace coming in from the left is the EN signal.

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One thing that worries me a little is that they're recommending a 4-layer design, and that's not an option for me (hobbyist level resources, both for layout and manufacture). How does that impact the layout consideration for the trace connecting the boost cap and the SW node?

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  • \$\begingroup\$ Related: Consider adding a "small" capacitor across R14 to improve response to transient load changes. You'll see that done in a number of other designs but certainly not all. You can analyse that formally - or view it as coupling load transients directly to the VFB pin. \$\endgroup\$
    – Russell McMahon ♦
    Sep 14, 2014 at 6:38
  • \$\begingroup\$ your layout is identical to the recommended one, it will work seamlessly... provided their worked. I have not much experience with making layouts for DCDC (just a couple of boards), but I feel that all the difficulty associated with them is a bit overrated. Ok, you need to pay attention but that's not a LVDS bus for some DDR4 in the giga ballpark. It will work. \$\endgroup\$
    – Vladimir Cravero
    Sep 14, 2014 at 9:26
  • \$\begingroup\$ @RussellMcMahon what would you consider small? .1uF? Smaller? And I assume layout-wise it should sit right on top of R14? \$\endgroup\$
    – kolosy
    Sep 14, 2014 at 17:26
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    \$\begingroup\$ @kolosy Very smallish / look at designs that do this /"Select on test"/Other ... :-). Probably 1 nanofarad or less. "Near" R14 is fine. Nearer the better, but liable to be substantially larger than stray capacitances so only somewhat influenced thereby. Any track length is inductance but again probably not too large. \$\endgroup\$
    – Russell McMahon ♦
    Sep 14, 2014 at 18:47

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I've looked at it for 10 minutes, and it doesn't look too bad. It's good that there is a recommended layout and you've found it.

  • Put C32 vertically between C18 and the regulator.
  • I would put the the feedback network above the regulator, rather than below. it would be shorter. Also, you'll have easier time keeping it in the top layer. (Recommended layout diagram has the feedback network routed above the controller too.)
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  • \$\begingroup\$ Cool. One concern - putting C32 where you suggest would require moving the inductor and C17 and 18 farther away from the regulator. Do you think that's an issue? They say to keep the trace from SW to the inductor as short as possible. Another option would be to combine C17 and 18 into a single 22uF cap, and put C32 in that space.. \$\endgroup\$
    – kolosy
    Sep 14, 2014 at 3:22

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