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I'm trying hard to understand the different modes and regions of operation of BJTs. The behavior of transistor in saturation region is so confusing. I've searched in forums but couldn't get a convincing answer. Here is what I've understood. Correct me if I'm wrong.

So a Transistor enters saturation region when the collector-base junction is forward biased. This happens when the base current increases causing a proportionate increase in the collector current and decrease in voltage across the collector (\$V_{CE} = V_{CC} - I_CR_C\$).

What happens after the transistor enters saturation? I know that \$V_{CE}\$ will be very small (around 0.2V) and the transistor will behave as a closed switch. But what exactly will be the collector current?

Can I now view this as two back to back forward biased diodes?

Why is the current will be maximum in saturation region? Why doesn't further increase in base current cause changes in collector current?

And if you see the \$V_{CE}\$ characteristics in the saturation region (see the image below), the curves are bunched together. \$I_C\$ actually approaches zero as \$V_{CE}\$ is around 0.2V (which is nearly the voltage across collector in saturation). But should we not have maximum current in saturation region?

I'm missing some crucial point. The characteristic curves in Saturation region are completely confusing. Help me understand this :(

CE characteristic Curves

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  • \$\begingroup\$ @VladimirCravero sorry for the crappy edit, I'll give up on editing on my phone! It doesn't like leaving the subject alone for some reason... \$\endgroup\$ – Xcodo Sep 16 '14 at 8:25
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It can be confusing because in a MOSFET the saturation region is something else and they call the "linear" region what would be the "saturation" region in a BJT. Why oh why?

Here's my simplified picture of things for a BJT: -

enter image description here

Note that all the curves for different base currents do not overlap as is commonly shown. If they did overlap there would be no BJT based 4-quadrant multipliers (Gilbert cell). They rely on the saturation region being able to modulate the current for a given CE voltage. Anyway, that's a bit off the mark for your question.

The saturation region does include the scenario when CB is forward biased but I don't think this is particularly helpful - the saturation region (or close to it) must still encompass normal transistor amplification and, as far as I know, this cannot happen when collector and base are forward biased.

Why doesn't further increase in base current cause changes in collector current?

It does up till the point when the collector-base junction is forward biased. The curves look bunched in your diagram (and this is an error basically) but they are still different and for a given low voltage across C-E, the current is proportional to that voltage AND the base current.

Hope this helps.

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  • \$\begingroup\$ I still don't get it. Could you please explain? \$\endgroup\$ – Aditya Patil Sep 16 '14 at 10:43
  • \$\begingroup\$ I don't get what you don't get so, given my attempt at an answer, is there something for me to focus on specifically? \$\endgroup\$ – Andy aka Sep 16 '14 at 10:45
  • \$\begingroup\$ "It can be confusing because in a MOSFET the saturation region is something else... Why oh why?" Yes - indeed. I think, it is because of historical reasons only. One should ask: What or who is saturated? \$\endgroup\$ – LvW Sep 16 '14 at 11:02
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But should we not have maximum current in saturation region? I'm missing some crucial point. The characteristic curves in Saturation region are completely confusing.

The plot is of \$I_C\$ versus \$V_{CE}\$ with \$I_B\$ as a parameter.

For such a plot, \$V_{CE}\$ is the independent variable which is to say that it can be adjusted independent of the \$I_C\$.

schematic

simulate this circuit – Schematic created using CircuitLab

In other words, for this plot, the equation

$$V_{CE} = V_{CC} - I_C R_C$$

doesn't hold and I suspect this is why you find the plot confusing. Clearly, if you plot the above equation, you'll get a negative slope with \$I_C\$ decreasing as \$V_{CE}\$ increases with the maximum collector current given by

$$I_{C,max} = \frac{V_{CC} - V_{CE,sat}}{R_C} $$

which is, I suspect, what you were expecting.

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